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git01.mediatek.com / filogic / uboot / 578bac04de3428cbd5112f2d6abcbb04aeca871e / . / arch / arm / include / asm / arch-mx31 / imx-regs.h
blob: 552c8214e47ee7c0b9df3e1416a14c0b6630ff64 [file] [log] [blame]
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]1/*
2 *
3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Fabio Estevam4e01c432011-04-15 16:54:50 +0000[diff] [blame]24#ifndef __ASM_ARCH_MX31_IMX_REGS_H
25#define __ASM_ARCH_MX31_IMX_REGS_H
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]26
Magnus Lilja713532e2009-11-11 20:18:42 +0100[diff] [blame]27#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
28#include <asm/types.h>
29
30/* Clock control module registers */
31struct clock_control_regs {
32 u32 ccmr;
33 u32 pdr0;
34 u32 pdr1;
35 u32 rcsr;
36 u32 mpctl;
37 u32 upctl;
38 u32 spctl;
39 u32 cosr;
40 u32 cgr0;
41 u32 cgr1;
42 u32 cgr2;
43 u32 wimr0;
44 u32 ldc;
45 u32 dcvr0;
46 u32 dcvr1;
47 u32 dcvr2;
48 u32 dcvr3;
49 u32 ltr0;
50 u32 ltr1;
51 u32 ltr2;
52 u32 ltr3;
53 u32 ltbr0;
54 u32 ltbr1;
55 u32 pmcr0;
56 u32 pmcr1;
57 u32 pdr2;
58};
59
Stefano Babic28580452011-01-19 22:46:33 +0000[diff] [blame]60struct cspi_regs {
61 u32 rxdata;
62 u32 txdata;
63 u32 ctrl;
64 u32 intr;
65 u32 dma;
66 u32 stat;
67 u32 period;
68 u32 test;
69};
70
Stefano Babice17e3312011-02-02 00:49:36 +0000[diff] [blame]71/* Watchdog Timer (WDOG) registers */
72#define WDOG_ENABLE (1 << 2)
73#define WDOG_WT_SHIFT 8
Fabio Estevama335af92011-09-21 03:29:17 +0000[diff] [blame]74#define WDOG_WDZST (1 << 0)
75
Stefano Babice17e3312011-02-02 00:49:36 +0000[diff] [blame]76struct wdog_regs {
77 u16 wcr; /* Control */
78 u16 wsr; /* Service */
79 u16 wrsr; /* Reset Status */
80};
81
Fabio Estevam939b9782011-04-11 16:18:12 +0000[diff] [blame]82/* IIM Control Registers */
83struct iim_regs {
84 u32 iim_stat;
85 u32 iim_statm;
86 u32 iim_err;
87 u32 iim_emask;
88 u32 iim_fctl;
89 u32 iim_ua;
90 u32 iim_la;
91 u32 iim_sdat;
92 u32 iim_prev;
93 u32 iim_srev;
94 u32 iim_prog_p;
95 u32 iim_scs0;
96 u32 iim_scs1;
97 u32 iim_scs2;
98 u32 iim_scs3;
99};
100
101struct mx3_cpu_type {
102 u8 srev;
Stefano Babic7f5a0262011-04-29 08:56:27 +0200[diff] [blame]103 u32 v;
Fabio Estevam939b9782011-04-11 16:18:12 +0000[diff] [blame]104};
Stefano Babice17e3312011-02-02 00:49:36 +0000[diff] [blame]105
Stefano Babic6272c7e2010-10-06 08:59:26 +0200[diff] [blame]106#define IOMUX_PADNUM_MASK 0x1ff
107#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
108
109/*
110 * various IOMUX pad functions
111 */
112enum iomux_pad_config {
113 PAD_CTL_NOLOOPBACK = 0x0 << 9,
114 PAD_CTL_LOOPBACK = 0x1 << 9,
115 PAD_CTL_PKE_NONE = 0x0 << 8,
116 PAD_CTL_PKE_ENABLE = 0x1 << 8,
117 PAD_CTL_PUE_KEEPER = 0x0 << 7,
118 PAD_CTL_PUE_PUD = 0x1 << 7,
119 PAD_CTL_100K_PD = 0x0 << 5,
120 PAD_CTL_100K_PU = 0x1 << 5,
121 PAD_CTL_47K_PU = 0x2 << 5,
122 PAD_CTL_22K_PU = 0x3 << 5,
123 PAD_CTL_HYS_CMOS = 0x0 << 4,
124 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
125 PAD_CTL_ODE_CMOS = 0x0 << 3,
126 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
127 PAD_CTL_DRV_NORMAL = 0x0 << 1,
128 PAD_CTL_DRV_HIGH = 0x1 << 1,
129 PAD_CTL_DRV_MAX = 0x2 << 1,
130 PAD_CTL_SRE_SLOW = 0x0 << 0,
131 PAD_CTL_SRE_FAST = 0x1 << 0
132};
133
134/*
135 * This enumeration is constructed based on the Section
136 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
137 * value is constructed based on the rules described above.
138 */
139
140enum iomux_pins {
141 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
142 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
143 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
144 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
145 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
146 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
147 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
148 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
149 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
150 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
151 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
152 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
153 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
154 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
155 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
156 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
157 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
158 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
159 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
160 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
161 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
162 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
163 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
164 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
165 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
166 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
167 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
168 MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
169 MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
170 MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
171 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
172 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
173 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
174 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
175 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
176 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
177 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
178 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
179 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
180 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
181 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
182 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
183 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
184 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
185 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
186 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
187 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
188 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
189 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
190 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
191 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
192 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
193 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
194 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
195 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
196 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
197 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
198 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
199 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
200 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
201 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
202 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
203 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
204 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
205 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
206 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
207 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
208 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
209 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
210 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
211 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
212 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
213 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
214 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
215 MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
216 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
217 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
218 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
219 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
220 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
221 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
222 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
223 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
224 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
225 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
226 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
227 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
228 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
229 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
230 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
231 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
232 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
233 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
234 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
235 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
236 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
237 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
238 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
239 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
240 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
241 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
242 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
243 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
244 MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
245 MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
246 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
247 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
248 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
249 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
250 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
251 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
252 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
253 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
254 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
255 MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
256 MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
257 MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
258 MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
259 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
260 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
261 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
262 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
263 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
264 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
265 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
266 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
267 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
268 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
269 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
270 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
271 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
272 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
273 MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
274 MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
275 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
276 MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
277 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
278 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
279 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
280 MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
281 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
282 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
283 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
284 MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
285 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
286 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
287 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
288 MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
289 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
290 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
291 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
292 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
293 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
294 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
295 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
296 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
297 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
298 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
299 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
300 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
301 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
302 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
303 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
304 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
305 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
306 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
307 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
308 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
309 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
310 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
311 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
312 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
313 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
314 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
315 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
316 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
317 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
318 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
319 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
320 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
321 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
322 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
323 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
324 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
325 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
326 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
327 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
328 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
329 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
330 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
331 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
332 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
333 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
334 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
335 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
336 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
337 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
338 MX31_PIN_NFRB = IOMUX_PIN(16, 197),
339 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
340 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
341 MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
342 MX31_PIN_NFALE = IOMUX_PIN(12, 201),
343 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
344 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
345 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
346 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
347 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
348 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
349 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
350 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
351 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
352 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
353 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
354 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
355 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
356 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
357 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
358 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
359 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
360 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
361 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
362 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
363 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
364 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
365 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
366 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
367 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
368 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
369 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
370 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
371 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
372 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
373 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
374 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
375 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
376 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
377 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
378 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
379 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
380 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
381 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
382 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
383 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
384 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
385 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
386 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
387 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
388 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
389 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
390 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
391 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
392 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
393 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
394 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
395 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
396 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
397 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
398 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
399 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
400 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
401 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
402 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
403 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
404 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
405 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
406 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
407 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
408 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
409 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
410 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
411 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
412 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
413 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
414 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
415 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
416 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
417 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
418 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
419 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
420 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
421 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
422 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
423 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
424 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
425 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
426 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
427 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
428 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
429 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
430 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
431 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
432 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
433 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
434 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
435 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
436 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
437 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
438 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
439 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
440 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
441 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
442 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
443 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
444 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
445 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
446 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
447 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
448 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
449 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
450 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
451 MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
452 MX31_PIN_STX0 = IOMUX_PIN(33, 311),
453 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
454 MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
455 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
456 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
457 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
458 MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317),
459 MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318),
460 MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319),
461 MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320),
462 MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321),
463 MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322),
464 MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
465 MX31_PIN_PWMO = IOMUX_PIN(9, 324),
466 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
467 MX31_PIN_COMPARE = IOMUX_PIN(8, 326),
468 MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
469};
Stefano Babicd77fe992010-07-06 17:05:06 +0200[diff] [blame]470
Magnus Lilja713532e2009-11-11 20:18:42 +0100[diff] [blame]471/* Bit definitions for RCSR register in CCM */
472#define CCM_RCSR_NF16B (1 << 31)
473#define CCM_RCSR_NFMS (1 << 30)
474
Helmut Raiger035929c2011-09-29 05:45:03 +0000[diff] [blame]475/* WEIM CS control registers */
476struct mx31_weim_cscr {
477 u32 upper;
478 u32 lower;
479 u32 additional;
480 u32 reserved;
481};
482
483struct mx31_weim {
484 struct mx31_weim_cscr cscr[6];
485};
486
Magnus Lilja713532e2009-11-11 20:18:42 +0100[diff] [blame]487#endif
488
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]489#define __REG(x) (*((volatile u32 *)(x)))
490#define __REG16(x) (*((volatile u16 *)(x)))
491#define __REG8(x) (*((volatile u8 *)(x)))
492
493#define CCM_BASE 0x53f80000
494#define CCM_CCMR (CCM_BASE + 0x00)
495#define CCM_PDR0 (CCM_BASE + 0x04)
496#define CCM_PDR1 (CCM_BASE + 0x08)
497#define CCM_RCSR (CCM_BASE + 0x0c)
498#define CCM_MPCTL (CCM_BASE + 0x10)
Maxim Artamonovfd24e752008-12-03 05:38:17 +0300[diff] [blame]499#define CCM_UPCTL (CCM_BASE + 0x14)
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]500#define CCM_SPCTL (CCM_BASE + 0x18)
501#define CCM_COSR (CCM_BASE + 0x1C)
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200[diff] [blame]502#define CCM_CGR0 (CCM_BASE + 0x20)
503#define CCM_CGR1 (CCM_BASE + 0x24)
504#define CCM_CGR2 (CCM_BASE + 0x28)
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]505
506#define CCMR_MDS (1 << 7)
507#define CCMR_SBYCS (1 << 4)
508#define CCMR_MPE (1 << 3)
509#define CCMR_PRCS_MASK (3 << 1)
510#define CCMR_FPM (1 << 1)
511#define CCMR_CKIH (2 << 1)
512
Fabio Estevam939b9782011-04-11 16:18:12 +0000[diff] [blame]513#define MX31_IIM_BASE_ADDR 0x5001C000
514
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]515#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
516#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
517#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
518#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
519#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
520#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
521#define PDR0_MCU_PODF(x) ((x) & 0x7)
522
523#define PLL_PD(x) (((x) & 0xf) << 26)
524#define PLL_MFD(x) (((x) & 0x3ff) << 16)
525#define PLL_MFI(x) (((x) & 0xf) << 10)
526#define PLL_MFN(x) (((x) & 0x3ff) << 0)
527
Helmut Raigerabd23432011-10-12 23:08:30 +0200[diff] [blame]528#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff)
529#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
530#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
531#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
532#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3)
533#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7)
534#define GET_PDR0_MCU_PODF(x) ((x) & 0x7)
535
536#define GET_PLL_PD(x) (((x) >> 26) & 0xf)
537#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff)
538#define GET_PLL_MFI(x) (((x) >> 10) & 0xf)
539#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff)
540
541
Magnus Lilja24f8b412009-07-04 10:31:24 +0200[diff] [blame]542#define WEIM_ESDCTL0 0xB8001000
543#define WEIM_ESDCFG0 0xB8001004
544#define WEIM_ESDCTL1 0xB8001008
545#define WEIM_ESDCFG1 0xB800100C
546#define WEIM_ESDMISC 0xB8001010
547
548#define ESDCTL_SDE (1 << 31)
549#define ESDCTL_CMD_RW (0 << 28)
550#define ESDCTL_CMD_PRECHARGE (1 << 28)
551#define ESDCTL_CMD_AUTOREFRESH (2 << 28)
552#define ESDCTL_CMD_LOADMODEREG (3 << 28)
553#define ESDCTL_CMD_MANUALREFRESH (4 << 28)
554#define ESDCTL_ROW_13 (2 << 24)
555#define ESDCTL_ROW(x) ((x) << 24)
556#define ESDCTL_COL_9 (1 << 20)
557#define ESDCTL_COL(x) ((x) << 20)
558#define ESDCTL_DSIZ(x) ((x) << 16)
559#define ESDCTL_SREFR(x) ((x) << 13)
560#define ESDCTL_PWDT(x) ((x) << 10)
561#define ESDCTL_FP(x) ((x) << 8)
562#define ESDCTL_BL(x) ((x) << 7)
563#define ESDCTL_PRCT(x) ((x) << 0)
564
Helmut Raiger035929c2011-09-29 05:45:03 +0000[diff] [blame]565/* 13 fields of the upper CS control register */
566#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
567 cnc, wsc, ew, wws, edc) \
568 ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
569 (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
570 (wws) << 4 | (edc) << 0)
571/* 12 fields of the lower CS control register */
572#define CSCR_L(oea, oen, ebwa, ebwn, \
573 csa, ebc, dsz, csn, psr, cre, wrap, csen) \
574 ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
575 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
576 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
577/* 14 fields of the additional CS control register */
578#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
579 wwu, age, cnc2, fce) \
580 ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
581 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
582 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
583 (age) << 2 | (cnc2) << 1 | (fce) << 0)
584
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]585#define WEIM_BASE 0xb8002000
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]586
587#define IOMUXC_BASE 0x43FAC000
588#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
589#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
590#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
591
592#define IPU_BASE 0x53fc0000
593#define IPU_CONF IPU_BASE
594
595#define IPU_CONF_PXL_ENDIAN (1<<8)
596#define IPU_CONF_DU_EN (1<<7)
597#define IPU_CONF_DI_EN (1<<6)
598#define IPU_CONF_ADC_EN (1<<5)
599#define IPU_CONF_SDC_EN (1<<4)
600#define IPU_CONF_PF_EN (1<<3)
601#define IPU_CONF_ROT_EN (1<<2)
602#define IPU_CONF_IC_EN (1<<1)
603#define IPU_CONF_SCI_EN (1<<0)
604
Magnus Lilja6eeb6f72009-07-01 01:07:55 +0200[diff] [blame]605#define ARM_PPMRR 0x40000015
606
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]607#define WDOG_BASE 0x53FDC000
608
609/*
Ilya Yanokbd296952009-02-08 00:59:43 +0300[diff] [blame]610 * GPIO
611 */
Stefano Babicd77fe992010-07-06 17:05:06 +0200[diff] [blame]612#define GPIO1_BASE_ADDR 0x53FCC000
613#define GPIO2_BASE_ADDR 0x53FD0000
614#define GPIO3_BASE_ADDR 0x53FA4000
Ilya Yanokbd296952009-02-08 00:59:43 +0300[diff] [blame]615#define GPIO_DR 0x00000000 /* data register */
616#define GPIO_GDIR 0x00000004 /* direction register */
617#define GPIO_PSR 0x00000008 /* pad status register */
618
619/*
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]620 * Signal Multiplexing (IOMUX)
621 */
622
623/* bits in the SW_MUX_CTL registers */
624#define MUX_CTL_OUT_GPIO_DR (0 << 4)
625#define MUX_CTL_OUT_FUNC (1 << 4)
626#define MUX_CTL_OUT_ALT1 (2 << 4)
627#define MUX_CTL_OUT_ALT2 (3 << 4)
628#define MUX_CTL_OUT_ALT3 (4 << 4)
629#define MUX_CTL_OUT_ALT4 (5 << 4)
630#define MUX_CTL_OUT_ALT5 (6 << 4)
631#define MUX_CTL_OUT_ALT6 (7 << 4)
632#define MUX_CTL_IN_NONE (0 << 0)
633#define MUX_CTL_IN_GPIO (1 << 0)
634#define MUX_CTL_IN_FUNC (2 << 0)
635#define MUX_CTL_IN_ALT1 (4 << 0)
636#define MUX_CTL_IN_ALT2 (8 << 0)
637
638#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
639#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
640#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
641#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
642
643/* Register offsets based on IOMUXC_BASE */
644/* 0x00 .. 0x7b */
Stefano Babic6272c7e2010-10-06 08:59:26 +0200[diff] [blame]645#define MUX_CTL_USBH2_DATA1 0x40
646#define MUX_CTL_USBH2_DIR 0x44
647#define MUX_CTL_USBH2_STP 0x45
648#define MUX_CTL_USBH2_NXT 0x46
649#define MUX_CTL_USBH2_DATA0 0x47
650#define MUX_CTL_USBH2_CLK 0x4B
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]651#define MUX_CTL_RTS1 0x7c
652#define MUX_CTL_CTS1 0x7d
653#define MUX_CTL_DTR_DCE1 0x7e
654#define MUX_CTL_DSR_DCE1 0x7f
655#define MUX_CTL_CSPI2_SCLK 0x80
656#define MUX_CTL_CSPI2_SPI_RDY 0x81
657#define MUX_CTL_RXD1 0x82
658#define MUX_CTL_TXD1 0x83
659#define MUX_CTL_CSPI2_MISO 0x84
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200[diff] [blame]660#define MUX_CTL_CSPI2_SS0 0x85
661#define MUX_CTL_CSPI2_SS1 0x86
662#define MUX_CTL_CSPI2_SS2 0x87
Guennadi Liakhovetskie99f10a2009-02-24 10:44:02 +0100[diff] [blame]663#define MUX_CTL_CSPI1_SS2 0x88
664#define MUX_CTL_CSPI1_SCLK 0x89
665#define MUX_CTL_CSPI1_SPI_RDY 0x8a
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]666#define MUX_CTL_CSPI2_MOSI 0x8b
Guennadi Liakhovetskie99f10a2009-02-24 10:44:02 +0100[diff] [blame]667#define MUX_CTL_CSPI1_MOSI 0x8c
668#define MUX_CTL_CSPI1_MISO 0x8d
669#define MUX_CTL_CSPI1_SS0 0x8e
670#define MUX_CTL_CSPI1_SS1 0x8f
Stefano Babicbc86e0f2010-10-01 12:34:34 +0200[diff] [blame]671#define MUX_CTL_STXD6 0x90
672#define MUX_CTL_SRXD6 0x91
673#define MUX_CTL_SCK6 0x92
674#define MUX_CTL_SFS6 0x93
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]675
Stefano Babic6272c7e2010-10-06 08:59:26 +0200[diff] [blame]676#define MUX_CTL_STXD3 0x9C
677#define MUX_CTL_SRXD3 0x9D
678#define MUX_CTL_SCK3 0x9E
679#define MUX_CTL_SFS3 0x9F
680
Stefano Babic52492d72010-03-29 15:56:10 +0200[diff] [blame]681#define MUX_CTL_NFC_WP 0xD0
682#define MUX_CTL_NFC_CE 0xD1
683#define MUX_CTL_NFC_RB 0xD2
684#define MUX_CTL_NFC_WE 0xD4
685#define MUX_CTL_NFC_RE 0xD5
686#define MUX_CTL_NFC_ALE 0xD6
687#define MUX_CTL_NFC_CLE 0xD7
688
689
Stefano Babicbc86e0f2010-10-01 12:34:34 +0200[diff] [blame]690#define MUX_CTL_CAPTURE 0x150
691#define MUX_CTL_COMPARE 0x151
692
Magnus Lilja532c1582008-08-03 21:44:10 +0200[diff] [blame]693/*
694 * Helper macros for the MUX_[contact name]__[pin function] macros
695 */
696#define IOMUX_MODE_POS 9
697#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
698
699/*
700 * These macros can be used in mx31_gpio_mux() and have the form
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]701 * MUX_[contact name]__[pin function]
702 */
Magnus Lilja532c1582008-08-03 21:44:10 +0200[diff] [blame]703#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
704#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
705#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
706#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
707
708#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
709#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
710#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
711#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
712#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
713#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
714 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
715#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]716
Guennadi Liakhovetskie99f10a2009-02-24 10:44:02 +0100[diff] [blame]717#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
718#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
719#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
720#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
721#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
722#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
723 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
724#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
725
Magnus Lilja532c1582008-08-03 21:44:10 +0200[diff] [blame]726#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
727#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]728
Magnus Lilja24f8b412009-07-04 10:31:24 +0200[diff] [blame]729/* PAD control registers for SDR/DDR */
730#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
731#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
732#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
733#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
734#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
735#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
736#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
737#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
738#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
739#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
740#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
741#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
742#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
743#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
744#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
745#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
746#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
747#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
748#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
749#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
750#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
751#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
752#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
753#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
754#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
755#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
756#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
757#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
758#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
759
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200[diff] [blame]760/*
761 * Memory regions and CS
762 */
763#define IPU_MEM_BASE 0x70000000
764#define CSD0_BASE 0x80000000
765#define CSD1_BASE 0x90000000
766#define CS0_BASE 0xA0000000
767#define CS1_BASE 0xA8000000
768#define CS2_BASE 0xB0000000
769#define CS3_BASE 0xB2000000
770#define CS4_BASE 0xB4000000
771#define CS4_PSRAM_BASE 0xB5000000
772#define CS5_BASE 0xB6000000
773#define PCMCIA_MEM_BASE 0xC0000000
Sascha Hauer1a7676f2008-03-26 20:40:42 +0100[diff] [blame]774
Magnus Lilja4133f652009-06-13 20:50:01 +0200[diff] [blame]775/*
776 * NAND controller
777 */
778#define NFC_BASE_ADDR 0xB8000000
779
Stefano Babicbd9280e2010-03-31 10:27:47 +0200[diff] [blame]780/*
781 * Internal RAM (16KB)
782 */
783#define IRAM_BASE_ADDR 0x1FFFC000
784#define IRAM_SIZE (16 * 1024)
785
Stefano Babic6272c7e2010-10-06 08:59:26 +0200[diff] [blame]786#define MX31_AIPS1_BASE_ADDR 0x43f00000
Matthias Weisserdba1f9b2011-07-06 00:28:30 +0000[diff] [blame]787#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
Stefano Babic6272c7e2010-10-06 08:59:26 +0200[diff] [blame]788
789/* USB portsc */
790/* values for portsc field */
791#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
792#define MXC_EHCI_FORCE_FS (1 << 24)
793#define MXC_EHCI_UTMI_8BIT (0 << 28)
794#define MXC_EHCI_UTMI_16BIT (1 << 28)
795#define MXC_EHCI_SERIAL (1 << 29)
796#define MXC_EHCI_MODE_UTMI (0 << 30)
797#define MXC_EHCI_MODE_PHILIPS (1 << 30)
798#define MXC_EHCI_MODE_ULPI (2 << 30)
799#define MXC_EHCI_MODE_SERIAL (3 << 30)
800
801/* values for flags field */
802#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
803#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
804#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
805#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
806#define MXC_EHCI_INTERFACE_MASK (0xf)
807
808#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
809#define MXC_EHCI_TTL_ENABLED (1 << 6)
810
811#define MXC_EHCI_INTERNAL_PHY (1 << 7)
812#define MXC_EHCI_IPPUE_DOWN (1 << 8)
813#define MXC_EHCI_IPPUE_UP (1 << 9)
814
Fabio Estevam4e01c432011-04-15 16:54:50 +0000[diff] [blame]815#endif /* __ASM_ARCH_MX31_IMX_REGS_H */