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Stelian Pop0bf5cad2008-05-08 18:52:25 +02001/*
2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * Common definitions.
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#ifndef AT91SAM9RL_H
15#define AT91SAM9RL_H
16
17/*
Xu, Hong16c092b2011-08-01 03:56:32 +000018 * Peripheral identifiers/interrupts.
19 */
20#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
21#define ATMEL_ID_SYS 1 /* System Peripherals */
22#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
23#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
24#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
25#define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */
26#define ATMEL_ID_USART0 6 /* USART 0 */
27#define ATMEL_ID_USART1 7 /* USART 1 */
28#define ATMEL_ID_USART2 8 /* USART 2 */
29#define ATMEL_ID_USART3 9 /* USART 3 */
30#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */
31#define ATMEL_ID_TWI0 11 /* TWI 0 */
32#define ATMEL_ID_TWI1 12 /* TWI 1 */
33#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */
34#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
36#define ATMEL_ID_TC0 16 /* Timer Counter 0 */
37#define ATMEL_ID_TC1 17 /* Timer Counter 1 */
38#define ATMEL_ID_TC2 18 /* Timer Counter 2 */
39#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
40#define ATMEL_ID_TSC 20 /* Touch Screen Controller */
41#define ATMEL_ID_DMA 21 /* DMA Controller */
42#define ATMEL_ID_UDPHS 22 /* USB Device HS */
43#define ATMEL_ID_LCDC 23 /* LCD Controller */
44#define ATMEL_ID_AC97C 24 /* AC97 Controller */
45#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020046
47/*
48 * User Peripheral physical base addresses.
49 */
Xu, Hong16c092b2011-08-01 03:56:32 +000050#define ATMEL_BASE_TCB0 0xfffa0000
51#define ATMEL_BASE_TC0 0xfffa0000
52#define ATMEL_BASE_TC1 0xfffa0040
53#define ATMEL_BASE_TC2 0xfffa0080
54#define ATMEL_BASE_MCI 0xfffa4000
55#define ATMEL_BASE_TWI0 0xfffa8000
56#define ATMEL_BASE_TWI1 0xfffac000
57#define ATMEL_BASE_USART0 0xfffb0000
58#define ATMEL_BASE_USART1 0xfffb4000
59#define ATMEL_BASE_USART2 0xfffb8000
60#define ATMEL_BASE_USART3 0xfffbc000
61#define ATMEL_BASE_SSC0 0xfffc0000
62#define ATMEL_BASE_SSC1 0xfffc4000
63#define ATMEL_BASE_PWMC 0xfffc8000
64#define ATMEL_BASE_SPI0 0xfffcc000
65#define ATMEL_BASE_TSC 0xfffd0000
66#define ATMEL_BASE_UDPHS 0xfffd4000
67#define ATMEL_BASE_AC97C 0xfffd8000
68#define ATMEL_BASE_SYS 0xffffc000
Stelian Pop0bf5cad2008-05-08 18:52:25 +020069
Stelian Pop0bf5cad2008-05-08 18:52:25 +020070/*
Xu, Hong16c092b2011-08-01 03:56:32 +000071 * System Peripherals
Stelian Pop0bf5cad2008-05-08 18:52:25 +020072 */
Xu, Hong16c092b2011-08-01 03:56:32 +000073#define ATMEL_BASE_DMA 0xffffe600
74#define ATMEL_BASE_ECC 0xffffe800
75#define ATMEL_BASE_SDRAMC 0xffffea00
76#define ATMEL_BASE_SMC 0xffffec00
77#define ATMEL_BASE_MATRIX 0xffffee00
78#define ATMEL_BASE_CCFG 0xffffef10
79#define ATMEL_BASE_AIC 0xfffff000
80#define ATMEL_BASE_DBGU 0xfffff200
81#define ATMEL_BASE_PIOA 0xfffff400
82#define ATMEL_BASE_PIOB 0xfffff600
83#define ATMEL_BASE_PIOC 0xfffff800
84#define ATMEL_BASE_PIOD 0xfffffa00
85#define ATMEL_BASE_PMC 0xfffffc00
86#define ATMEL_BASE_RSTC 0xfffffd00
87#define ATMEL_BASE_SHDWC 0xfffffd10
88#define ATMEL_BASE_RTT 0xfffffd20
89#define ATMEL_BASE_PIT 0xfffffd30
90#define ATMEL_BASE_WDT 0xfffffd40
91#define ATMEL_BASE_SCKCR 0xfffffd50
92#define ATMEL_BASE_GPBR 0xfffffd60
93#define ATMEL_BASE_RTC 0xfffffe00
Stelian Pop0bf5cad2008-05-08 18:52:25 +020094
95/*
96 * Internal Memory.
97 */
Xu, Hong16c092b2011-08-01 03:56:32 +000098#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
99#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200100
Xu, Hong16c092b2011-08-01 03:56:32 +0000101#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
102#define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */
103
104/*
105 * External memory
106 */
107#define ATMEL_BASE_CS0 0x10000000
108#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
109#define ATMEL_BASE_CS2 0x30000000
110#define ATMEL_BASE_CS3 0x40000000 /* NAND */
111#define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */
112#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200113
Bo Shen568079a2015-02-04 15:53:01 +0800114/* Timer */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500115#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
Bo Shen568079a2015-02-04 15:53:01 +0800116
Xu, Hong16c092b2011-08-01 03:56:32 +0000117/*
118 * Other misc defines
119 */
120#define ATMEL_PIO_PORTS 4 /* this SoC has 4 PIO */
121#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200122
Jean-Christophe PLAGNIOL-VILLARDb21aa662009-05-31 12:44:46 +0200123/*
124 * Cpu Name
125 */
Xu, Hong16c092b2011-08-01 03:56:32 +0000126#define ATMEL_CPU_NAME "AT91SAM9RL"
Jean-Christophe PLAGNIOL-VILLARDb21aa662009-05-31 12:44:46 +0200127
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200128#endif