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git01.mediatek.com / filogic / uboot / 86ddc967b259a5b73865663a741639fa7c3e032c / . / arch / arm / dts / stm32mp15xx-dhcor-drc-compact-u-boot.dtsi
blob: 038c3a92eb19cf51af65387deb6b0ba6ef361b79 [file] [log] [blame]
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "stm32mp15xx-dhcor-u-boot.dtsi"
7
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]8/ {
9 aliases {
10 mmc0 = &sdmmc1;
11 mmc1 = &sdmmc2;
12 usb0 = &usbotg_hs;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]13 };
14
15 config {
16 dh,board-coding-gpios = <&gpioh 9 0>, <&gpioh 8 0>, <&gpioh 3 0>;
17 };
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]18};
19
20&ethernet0 {
21 phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
22
23 mdio0 {
24 ethernet-phy@7 {
25 reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
26 reset-assert-us = <11000>;
27 reset-deassert-us = <1000>;
28 };
29 };
30};
31
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]32&sdmmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]34 st,use-ckin;
35 st,cmd-gpios = <&gpiod 2 0>;
36 st,ck-gpios = <&gpioc 12 0>;
37 st,ckin-gpios = <&gpioe 4 0>;
38};
39
40&sdmmc1_b4_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]42 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]44 };
45 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]47 };
48};
49
50&sdmmc1_dir_pins_b {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]52 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]54 };
55 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]57 };
58};
59
60&sdmmc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]62};
63
64&sdmmc2_b4_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]66 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]68 };
69 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]71 };
72};
73
74&sdmmc2_d47_pins_c {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]76 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]78 };
79};
80
81&sdmmc3 { /* SDIO Wi-Fi */
82 status = "disabled";
83};
84
85&uart4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-all;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]87};
88
89&uart4_pins_d {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-all;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]91 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-all;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]93 };
94 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-all;
Marek Vasute31d9872022-06-13 11:55:21 +0200[diff] [blame]96 /delete-property/ bias-disable;
97 bias-pull-up;
98 };
99};
100
101&usbotg_hs {
102 u-boot,force-b-session-valid;
103 hnp-srp-disable;
104};