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git01.mediatek.com / filogic / uboot / 86ddc967b259a5b73865663a741639fa7c3e032c / . / arch / arm / dts / nuvoton-common-npcm8xx.dtsi
blob: 1694ef8849520e67b52ca4e6eb0efb83d0b3047e [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
3
4#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/interrupt-controller/irq.h>
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]7#include <dt-bindings/gpio/gpio.h>
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]8
9/ {
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
13
14 soc {
15 #address-cells = <2>;
16 #size-cells = <2>;
17 compatible = "simple-bus";
18 interrupt-parent = <&gic>;
19 ranges;
20
21 gcr: system-controller@f0800000 {
22 compatible = "nuvoton,npcm845-gcr", "syscon";
23 reg = <0x0 0xf0800000 0x0 0x1000>;
24 };
25
26 gic: interrupt-controller@dfff9000 {
27 compatible = "arm,gic-400";
28 reg = <0x0 0xdfff9000 0x0 0x1000>,
29 <0x0 0xdfffa000 0x0 0x2000>,
30 <0x0 0xdfffc000 0x0 0x2000>,
31 <0x0 0xdfffe000 0x0 0x2000>;
32 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
33 #interrupt-cells = <3>;
34 interrupt-controller;
35 #address-cells = <0>;
36 ppi-partitions {
37 ppi_cluster0: interrupt-partition-0 {
38 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
39 };
40 };
41 };
42 };
43
44 ahb {
45 #address-cells = <2>;
46 #size-cells = <2>;
47 compatible = "simple-bus";
48 interrupt-parent = <&gic>;
49 ranges;
50
51 rstc: reset-controller@f0801000 {
52 compatible = "nuvoton,npcm845-reset";
53 reg = <0x0 0xf0801000 0x0 0x78>;
54 #reset-cells = <2>;
55 nuvoton,sysgcr = <&gcr>;
56 };
57
58 clk: clock-controller@f0801000 {
59 compatible = "nuvoton,npcm845-clk";
60 #clock-cells = <1>;
61 reg = <0x0 0xf0801000 0x0 0x1000>;
62 };
63
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]64 sdhci0: sdhci@f0842000 {
65 compatible = "nuvoton,npcm845-sdhci";
66 reg = <0x0 0xf0842000 0x0 0x100>;
67 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&clk NPCM8XX_CLK_AHB>;
69 clock-names = "clk_mmc";
70 pinctrl-names = "default";
71 pinctrl-0 = <&mmc8_pins
72 &mmc_pins>;
73 status = "disabled";
74 };
75
76 fiu0: spi@fb000000 {
77 compatible = "nuvoton,npcm845-fiu";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0x0 0xfb000000 0x0 0x1000>,
81 <0x0 0x80000000 0x0 0x10000000>;
82 reg-names = "control", "memory";
83 clocks = <&clk NPCM8XX_CLK_SPI0>;
84 clock-names = "clk_ahb";
85 status = "disabled";
86 };
87
88 fiu1: spi@fb002000 {
89 compatible = "nuvoton,npcm845-fiu";
90 #address-cells = <1>;
91 #size-cells = <0>;
92 reg = <0x0 0xfb002000 0x0 0x1000>,
93 <0x0 0x90000000 0x0 0x4000000>;
94 reg-names = "control", "memory";
95 clocks = <&clk NPCM8XX_CLK_SPI1>;
96 clock-names = "clk_spi1";
97 pinctrl-names = "default";
98 pinctrl-0 = <&spi1_pins>;
99 status = "disabled";
100 };
101
102 fiu3: spi@c0000000 {
103 compatible = "nuvoton,npcm845-fiu";
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <0x0 0xc0000000 0x0 0x1000>,
107 <0x0 0xA0000000 0x0 0x20000000>;
108 reg-names = "control", "memory";
109 clocks = <&clk NPCM8XX_CLK_SPI3>;
110 clock-names = "clk_spi3";
111 pinctrl-names = "default";
112 pinctrl-0 = <&spi3_pins>;
113 status = "disabled";
114 };
115
116 fiux: spi@fb001000 {
117 compatible = "nuvoton,npcm845-fiu";
118 #address-cells = <1>;
119 #size-cells = <0>;
120 reg = <0x0 0xfb001000 0x0 0x1000>,
121 <0x0 0xf8000000 0x0 0x2000000>;
122 reg-names = "control", "memory";
123 clocks = <&clk NPCM8XX_CLK_SPIX>;
124 clock-names = "clk_ahb";
125 status = "disabled";
126 };
127
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]128 apb {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 compatible = "simple-bus";
132 interrupt-parent = <&gic>;
133 ranges = <0x0 0x0 0xf0000000 0x00300000>,
134 <0xfff00000 0x0 0xfff00000 0x00016000>;
135
Jim Liu4ddc8d42023-11-14 16:51:56 +0800[diff] [blame]136 host_intf: host_intf@9f000 {
137 compatible = "nuvoton,npcm845-host-intf";
138 reg = <0x9f000 0x1000>;
139 type = "espi";
140 ioaddr = <0x4e>;
141 channel-support = <0xf>;
142 syscon = <&gcr>;
143 };
144
145 pspi: spi@201000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]146 compatible = "nuvoton,npcm845-pspi";
147 reg = <0x201000 0x1000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pspi_pins>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&clk NPCM8XX_CLK_APB5>;
154 clock-names = "clk_apb5";
155 status = "disabled";
156 };
157
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]158 timer0: timer@8000 {
159 compatible = "nuvoton,npcm845-timer";
160 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
161 reg = <0x8000 0x1C>;
162 clocks = <&clk NPCM8XX_CLK_REFCLK>;
163 clock-names = "refclk";
164 };
165
166 serial0: serial@0 {
167 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
168 reg = <0x0 0x1000>;
169 clocks = <&clk NPCM8XX_CLK_UART>;
170 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
171 reg-shift = <2>;
172 status = "disabled";
173 };
174
175 serial1: serial@1000 {
176 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
177 reg = <0x1000 0x1000>;
178 clocks = <&clk NPCM8XX_CLK_UART>;
179 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
180 reg-shift = <2>;
181 status = "disabled";
182 };
183
184 serial2: serial@2000 {
185 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
186 reg = <0x2000 0x1000>;
187 clocks = <&clk NPCM8XX_CLK_UART>;
188 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
189 reg-shift = <2>;
190 status = "disabled";
191 };
192
193 serial3: serial@3000 {
194 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
195 reg = <0x3000 0x1000>;
196 clocks = <&clk NPCM8XX_CLK_UART>;
197 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
198 reg-shift = <2>;
199 status = "disabled";
200 };
201
202 serial4: serial@4000 {
203 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
204 reg = <0x4000 0x1000>;
205 clocks = <&clk NPCM8XX_CLK_UART>;
206 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
207 reg-shift = <2>;
208 status = "disabled";
209 };
210
211 serial5: serial@5000 {
212 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
213 reg = <0x5000 0x1000>;
214 clocks = <&clk NPCM8XX_CLK_UART>;
215 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
216 reg-shift = <2>;
217 status = "disabled";
218 };
219
220 serial6: serial@6000 {
221 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
222 reg = <0x6000 0x1000>;
223 clocks = <&clk NPCM8XX_CLK_UART>;
224 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
225 reg-shift = <2>;
226 status = "disabled";
227 };
228
229 watchdog0: watchdog@801c {
230 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
231 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
232 reg = <0x801c 0x4>;
233 status = "disabled";
234 clocks = <&clk NPCM8XX_CLK_REFCLK>;
235 syscon = <&gcr>;
236 };
237
238 watchdog1: watchdog@901c {
239 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
240 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
241 reg = <0x901c 0x4>;
242 status = "disabled";
243 clocks = <&clk NPCM8XX_CLK_REFCLK>;
244 syscon = <&gcr>;
245 };
246
247 watchdog2: watchdog@a01c {
248 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
249 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
250 reg = <0xa01c 0x4>;
251 status = "disabled";
252 clocks = <&clk NPCM8XX_CLK_REFCLK>;
253 syscon = <&gcr>;
254 };
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]255
256 i2c0: i2c@80000 {
257 compatible = "nuvoton,npcm845-i2c";
258 reg = <0x80000 0x1000>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 clocks = <&clk NPCM8XX_CLK_APB2>;
262 clock-frequency = <100000>;
263 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&smb0_pins>;
266 syscon = <&gcr>;
267 status = "disabled";
268 };
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800[diff] [blame]269
270 i2c1: i2c@81000 {
271 compatible = "nuvoton,npcm845-i2c";
272 reg = <0x81000 0x1000>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 clocks = <&clk NPCM8XX_CLK_APB2>;
276 clock-frequency = <100000>;
277 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&smb1_pins>;
280 syscon = <&gcr>;
281 status = "disabled";
282 };
283
284 i2c2: i2c@82000 {
285 compatible = "nuvoton,npcm845-i2c";
286 reg = <0x82000 0x1000>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 clocks = <&clk NPCM8XX_CLK_APB2>;
290 clock-frequency = <100000>;
291 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&smb2_pins>;
294 syscon = <&gcr>;
295 status = "disabled";
296 };
297
298 i2c3: i2c@83000 {
299 compatible = "nuvoton,npcm845-i2c";
300 reg = <0x83000 0x1000>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 clocks = <&clk NPCM8XX_CLK_APB2>;
304 clock-frequency = <100000>;
305 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&smb3_pins>;
308 syscon = <&gcr>;
309 status = "disabled";
310 };
311
312 i2c4: i2c@84000 {
313 compatible = "nuvoton,npcm845-i2c";
314 reg = <0x84000 0x1000>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clocks = <&clk NPCM8XX_CLK_APB2>;
318 clock-frequency = <100000>;
319 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&smb4_pins>;
322 syscon = <&gcr>;
323 status = "disabled";
324 };
325
326 i2c5: i2c@85000 {
327 compatible = "nuvoton,npcm845-i2c";
328 reg = <0x85000 0x1000>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clocks = <&clk NPCM8XX_CLK_APB2>;
332 clock-frequency = <100000>;
333 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&smb5_pins>;
336 syscon = <&gcr>;
337 status = "disabled";
338 };
339
340 i2c6: i2c@86000 {
341 compatible = "nuvoton,npcm845-i2c";
342 reg = <0x86000 0x1000>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 clocks = <&clk NPCM8XX_CLK_APB2>;
346 clock-frequency = <100000>;
347 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&smb6_pins>;
350 syscon = <&gcr>;
351 status = "disabled";
352 };
353
354 i2c7: i2c@87000 {
355 compatible = "nuvoton,npcm845-i2c";
356 reg = <0x87000 0x1000>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 clocks = <&clk NPCM8XX_CLK_APB2>;
360 clock-frequency = <100000>;
361 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&smb7_pins>;
364 syscon = <&gcr>;
365 status = "disabled";
366 };
367
368 i2c8: i2c@88000 {
369 compatible = "nuvoton,npcm845-i2c";
370 reg = <0x88000 0x1000>;
371 #address-cells = <1>;
372 #size-cells = <0>;
373 clocks = <&clk NPCM8XX_CLK_APB2>;
374 clock-frequency = <100000>;
375 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&smb8_pins>;
378 syscon = <&gcr>;
379 status = "disabled";
380 };
381
382 i2c9: i2c@89000 {
383 compatible = "nuvoton,npcm845-i2c";
384 reg = <0x89000 0x1000>;
385 #address-cells = <1>;
386 #size-cells = <0>;
387 clocks = <&clk NPCM8XX_CLK_APB2>;
388 clock-frequency = <100000>;
389 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&smb9_pins>;
392 syscon = <&gcr>;
393 status = "disabled";
394 };
395
396 i2c10: i2c@8a000 {
397 compatible = "nuvoton,npcm845-i2c";
398 reg = <0x8a000 0x1000>;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 clocks = <&clk NPCM8XX_CLK_APB2>;
402 clock-frequency = <100000>;
403 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&smb10_pins>;
406 syscon = <&gcr>;
407 status = "disabled";
408 };
409
410 i2c11: i2c@8b000 {
411 compatible = "nuvoton,npcm845-i2c";
412 reg = <0x8b000 0x1000>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clocks = <&clk NPCM8XX_CLK_APB2>;
416 clock-frequency = <100000>;
417 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&smb11_pins>;
420 syscon = <&gcr>;
421 status = "disabled";
422 };
423
424 i2c12: i2c@8c000 {
425 compatible = "nuvoton,npcm845-i2c";
426 reg = <0x8c000 0x1000>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 clocks = <&clk NPCM8XX_CLK_APB2>;
430 clock-frequency = <100000>;
431 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&smb12_pins>;
434 syscon = <&gcr>;
435 status = "disabled";
436 };
437
438 i2c13: i2c@8d000 {
439 compatible = "nuvoton,npcm845-i2c";
440 reg = <0x8d000 0x1000>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 clocks = <&clk NPCM8XX_CLK_APB2>;
444 clock-frequency = <100000>;
445 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&smb13_pins>;
448 syscon = <&gcr>;
449 status = "disabled";
450 };
451
452 i2c14: i2c@8e000 {
453 compatible = "nuvoton,npcm845-i2c";
454 reg = <0x8e000 0x1000>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 clocks = <&clk NPCM8XX_CLK_APB2>;
458 clock-frequency = <100000>;
459 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&smb14_pins>;
462 syscon = <&gcr>;
463 status = "disabled";
464 };
465
466 i2c15: i2c@8f000 {
467 compatible = "nuvoton,npcm845-i2c";
468 reg = <0x8f000 0x1000>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471 clocks = <&clk NPCM8XX_CLK_APB2>;
472 clock-frequency = <100000>;
473 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&smb15_pins>;
476 syscon = <&gcr>;
477 status = "disabled";
478 };
479
480 i2c16: i2c@fff00000 {
481 compatible = "nuvoton,npcm845-i2c";
482 reg = <0xfff00000 0x1000>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 clocks = <&clk NPCM8XX_CLK_APB2>;
486 clock-frequency = <100000>;
487 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&smb16_pins>;
490 syscon = <&gcr>;
491 status = "disabled";
492 };
493
494 i2c17: i2c@fff01000 {
495 compatible = "nuvoton,npcm845-i2c";
496 reg = <0xfff01000 0x1000>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 clocks = <&clk NPCM8XX_CLK_APB2>;
500 clock-frequency = <100000>;
501 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&smb17_pins>;
504 syscon = <&gcr>;
505 status = "disabled";
506 };
507
508 i2c18: i2c@fff02000 {
509 compatible = "nuvoton,npcm845-i2c";
510 reg = <0xfff02000 0x1000>;
511 #address-cells = <1>;
512 #size-cells = <0>;
513 clocks = <&clk NPCM8XX_CLK_APB2>;
514 clock-frequency = <100000>;
515 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&smb18_pins>;
518 syscon = <&gcr>;
519 status = "disabled";
520 };
521
522 i2c19: i2c@fff03000 {
523 compatible = "nuvoton,npcm845-i2c";
524 reg = <0xfff03000 0x1000>;
525 #address-cells = <1>;
526 #size-cells = <0>;
527 clocks = <&clk NPCM8XX_CLK_APB2>;
528 clock-frequency = <100000>;
529 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&smb19_pins>;
532 syscon = <&gcr>;
533 status = "disabled";
534 };
535
536 i2c20: i2c@fff04000 {
537 compatible = "nuvoton,npcm845-i2c";
538 reg = <0xfff04000 0x1000>;
539 #address-cells = <1>;
540 #size-cells = <0>;
541 clocks = <&clk NPCM8XX_CLK_APB2>;
542 clock-frequency = <100000>;
543 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&smb20_pins>;
546 syscon = <&gcr>;
547 status = "disabled";
548 };
549
550 i2c21: i2c@fff05000 {
551 compatible = "nuvoton,npcm845-i2c";
552 reg = <0xfff05000 0x1000>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 clocks = <&clk NPCM8XX_CLK_APB2>;
556 clock-frequency = <100000>;
557 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&smb21_pins>;
560 syscon = <&gcr>;
561 status = "disabled";
562 };
563
564 i2c22: i2c@fff06000 {
565 compatible = "nuvoton,npcm845-i2c";
566 reg = <0xfff06000 0x1000>;
567 #address-cells = <1>;
568 #size-cells = <0>;
569 clocks = <&clk NPCM8XX_CLK_APB2>;
570 clock-frequency = <100000>;
571 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&smb22_pins>;
574 syscon = <&gcr>;
575 status = "disabled";
576 };
577
578 i2c23: i2c@fff07000 {
579 compatible = "nuvoton,npcm845-i2c";
580 reg = <0xfff07000 0x1000>;
581 #address-cells = <1>;
582 #size-cells = <0>;
583 clocks = <&clk NPCM8XX_CLK_APB2>;
584 clock-frequency = <100000>;
585 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&smb23_pins>;
588 syscon = <&gcr>;
589 status = "disabled";
590 };
591
592 i2c24: i2c@fff08000 {
593 compatible = "nuvoton,npcm845-i2c";
594 reg = <0xfff08000 0x1000>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597 clocks = <&clk NPCM8XX_CLK_APB2>;
598 clock-frequency = <100000>;
599 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
600 syscon = <&gcr>;
601 status = "disabled";
602 };
603
604 i2c25: i2c@fff09000 {
605 compatible = "nuvoton,npcm845-i2c";
606 reg = <0xfff09000 0x1000>;
607 #address-cells = <1>;
608 #size-cells = <0>;
609 clocks = <&clk NPCM8XX_CLK_APB2>;
610 clock-frequency = <100000>;
611 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
612 syscon = <&gcr>;
613 status = "disabled";
614 };
615
616 i2c26: i2c@fff0a000 {
617 compatible = "nuvoton,npcm845-i2c";
618 reg = <0xfff0a000 0x1000>;
619 #address-cells = <1>;
620 #size-cells = <0>;
621 clocks = <&clk NPCM8XX_CLK_APB2>;
622 clock-frequency = <100000>;
623 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
624 syscon = <&gcr>;
625 status = "disabled";
626 };
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]627 };
628 };
629};