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git01.mediatek.com / filogic / uboot / 868dc1dc9aede807f1e5e223546d44d2ada9a05a / . / arch / arm / dts / rk3568.dtsi
blob: 12a071e6790e62c12baca1db7bf4b1d318c86bd0 [file] [log] [blame]
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rk3568-cru.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/soc/rockchip,boot-mode.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15 compatible = "rockchip,rk3568";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 i2c5 = &i2c5;
33 serial0 = &uart0;
34 serial1 = &uart1;
35 serial2 = &uart2;
36 serial3 = &uart3;
37 serial4 = &uart4;
38 serial5 = &uart5;
39 serial6 = &uart6;
40 serial7 = &uart7;
41 serial8 = &uart8;
42 serial9 = &uart9;
43 };
44
45 cpus {
46 #address-cells = <2>;
47 #size-cells = <0>;
48
49 cpu0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a55";
52 reg = <0x0 0x0>;
53 clocks = <&scmi_clk 0>;
54 enable-method = "psci";
55 operating-points-v2 = <&cpu0_opp_table>;
56 };
57
58 cpu1: cpu@100 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a55";
61 reg = <0x0 0x100>;
62 enable-method = "psci";
63 operating-points-v2 = <&cpu0_opp_table>;
64 };
65
66 cpu2: cpu@200 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a55";
69 reg = <0x0 0x200>;
70 enable-method = "psci";
71 operating-points-v2 = <&cpu0_opp_table>;
72 };
73
74 cpu3: cpu@300 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a55";
77 reg = <0x0 0x300>;
78 enable-method = "psci";
79 operating-points-v2 = <&cpu0_opp_table>;
80 };
81 };
82
83 cpu0_opp_table: cpu0-opp-table {
84 compatible = "operating-points-v2";
85 opp-shared;
86
87 opp-408000000 {
88 opp-hz = /bits/ 64 <408000000>;
89 opp-microvolt = <900000 900000 1150000>;
90 clock-latency-ns = <40000>;
91 };
92
93 opp-600000000 {
94 opp-hz = /bits/ 64 <600000000>;
95 opp-microvolt = <900000 900000 1150000>;
96 };
97
98 opp-816000000 {
99 opp-hz = /bits/ 64 <816000000>;
100 opp-microvolt = <900000 900000 1150000>;
101 opp-suspend;
102 };
103
104 opp-1104000000 {
105 opp-hz = /bits/ 64 <1104000000>;
106 opp-microvolt = <900000 900000 1150000>;
107 };
108
109 opp-1416000000 {
110 opp-hz = /bits/ 64 <1416000000>;
111 opp-microvolt = <900000 900000 1150000>;
112 };
113
114 opp-1608000000 {
115 opp-hz = /bits/ 64 <1608000000>;
116 opp-microvolt = <975000 975000 1150000>;
117 };
118
119 opp-1800000000 {
120 opp-hz = /bits/ 64 <1800000000>;
121 opp-microvolt = <1050000 1050000 1150000>;
122 };
123
124 opp-1992000000 {
125 opp-hz = /bits/ 64 <1992000000>;
126 opp-microvolt = <1150000 1150000 1150000>;
127 };
128 };
129
130 firmware {
131 scmi: scmi {
132 compatible = "arm,scmi-smc";
133 arm,smc-id = <0x82000010>;
134 shmem = <&scmi_shmem>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137
138 scmi_clk: protocol@14 {
139 reg = <0x14>;
140 #clock-cells = <1>;
141 };
142 };
143
144 };
145
146 pmu {
147 compatible = "arm,cortex-a55-pmu";
148 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
152 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
153 };
154
155 psci {
156 compatible = "arm,psci-1.0";
157 method = "smc";
158 };
159
160 timer {
161 compatible = "arm,armv8-timer";
162 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
166 arm,no-tick-in-suspend;
167 };
168
169 xin24m: xin24m {
170 compatible = "fixed-clock";
171 clock-frequency = <24000000>;
172 clock-output-names = "xin24m";
173 #clock-cells = <0>;
174 };
175
176 xin32k: xin32k {
177 compatible = "fixed-clock";
178 clock-frequency = <32768>;
179 clock-output-names = "xin32k";
180 pinctrl-0 = <&clk32k_out0>;
181 pinctrl-names = "default";
182 #clock-cells = <0>;
183 };
184
185 sram@10f000 {
186 compatible = "mmio-sram";
187 reg = <0x0 0x0010f000 0x0 0x100>;
188
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges = <0 0x0 0x0010f000 0x100>;
192
193 scmi_shmem: sram@0 {
194 compatible = "arm,scmi-shmem";
195 reg = <0x0 0x100>;
196 };
197 };
198
199 gic: interrupt-controller@fd400000 {
200 compatible = "arm,gic-v3";
201 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
202 <0x0 0xfd460000 0 0x80000>; /* GICR */
203 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
204 interrupt-controller;
205 #interrupt-cells = <3>;
206 mbi-alias = <0x0 0xfd100000>;
207 mbi-ranges = <296 24>;
208 msi-controller;
209 };
210
211 pmugrf: syscon@fdc20000 {
212 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
213 reg = <0x0 0xfdc20000 0x0 0x10000>;
214 };
215
216 grf: syscon@fdc60000 {
217 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
218 reg = <0x0 0xfdc60000 0x0 0x10000>;
219 };
220
221 pmucru: clock-controller@fdd00000 {
222 compatible = "rockchip,rk3568-pmucru";
223 reg = <0x0 0xfdd00000 0x0 0x1000>;
224 #clock-cells = <1>;
225 #reset-cells = <1>;
226 };
227
228 cru: clock-controller@fdd20000 {
229 compatible = "rockchip,rk3568-cru";
230 reg = <0x0 0xfdd20000 0x0 0x1000>;
231 #clock-cells = <1>;
232 #reset-cells = <1>;
233 };
234
235 i2c0: i2c@fdd40000 {
236 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
237 reg = <0x0 0xfdd40000 0x0 0x1000>;
238 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
240 clock-names = "i2c", "pclk";
241 pinctrl-0 = <&i2c0_xfer>;
242 pinctrl-names = "default";
243 #address-cells = <1>;
244 #size-cells = <0>;
245 status = "disabled";
246 };
247
248 uart0: serial@fdd50000 {
249 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
250 reg = <0x0 0xfdd50000 0x0 0x100>;
251 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
253 clock-names = "baudclk", "apb_pclk";
254 dmas = <&dmac0 0>, <&dmac0 1>;
255 pinctrl-0 = <&uart0_xfer>;
256 pinctrl-names = "default";
257 reg-io-width = <4>;
258 reg-shift = <2>;
259 status = "disabled";
260 };
261
262 pwm0: pwm@fdd70000 {
263 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
264 reg = <0x0 0xfdd70000 0x0 0x10>;
265 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
266 clock-names = "pwm", "pclk";
267 pinctrl-0 = <&pwm0m0_pins>;
268 pinctrl-names = "active";
269 #pwm-cells = <3>;
270 status = "disabled";
271 };
272
273 pwm1: pwm@fdd70010 {
274 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
275 reg = <0x0 0xfdd70010 0x0 0x10>;
276 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
277 clock-names = "pwm", "pclk";
278 pinctrl-0 = <&pwm1m0_pins>;
279 pinctrl-names = "active";
280 #pwm-cells = <3>;
281 status = "disabled";
282 };
283
284 pwm2: pwm@fdd70020 {
285 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
286 reg = <0x0 0xfdd70020 0x0 0x10>;
287 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
288 clock-names = "pwm", "pclk";
289 pinctrl-0 = <&pwm2m0_pins>;
290 pinctrl-names = "active";
291 #pwm-cells = <3>;
292 status = "disabled";
293 };
294
295 pwm3: pwm@fdd70030 {
296 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
297 reg = <0x0 0xfdd70030 0x0 0x10>;
298 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
299 clock-names = "pwm", "pclk";
300 pinctrl-0 = <&pwm3_pins>;
301 pinctrl-names = "active";
302 #pwm-cells = <3>;
303 status = "disabled";
304 };
305
306 sdmmc2: mmc@fe000000 {
307 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
308 reg = <0x0 0xfe000000 0x0 0x4000>;
309 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
311 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
312 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
313 fifo-depth = <0x100>;
314 max-frequency = <150000000>;
315 resets = <&cru SRST_SDMMC2>;
316 reset-names = "reset";
317 status = "disabled";
318 };
319
320 sdmmc0: mmc@fe2b0000 {
321 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
322 reg = <0x0 0xfe2b0000 0x0 0x4000>;
323 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
325 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
326 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
327 fifo-depth = <0x100>;
328 max-frequency = <150000000>;
329 resets = <&cru SRST_SDMMC0>;
330 reset-names = "reset";
331 status = "disabled";
332 };
333
334 sdmmc1: mmc@fe2c0000 {
335 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
336 reg = <0x0 0xfe2c0000 0x0 0x4000>;
337 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
339 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
340 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
341 fifo-depth = <0x100>;
342 max-frequency = <150000000>;
343 resets = <&cru SRST_SDMMC1>;
344 reset-names = "reset";
345 status = "disabled";
346 };
347
348 sdhci: mmc@fe310000 {
349 compatible = "rockchip,rk3568-dwcmshc";
350 reg = <0x0 0xfe310000 0x0 0x10000>;
351 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
352 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
353 assigned-clock-rates = <200000000>, <24000000>;
354 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
355 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
356 <&cru TCLK_EMMC>;
357 clock-names = "core", "bus", "axi", "block", "timer";
358 status = "disabled";
359 };
360
361 dmac0: dmac@fe530000 {
362 compatible = "arm,pl330", "arm,primecell";
363 reg = <0x0 0xfe530000 0x0 0x4000>;
364 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
366 arm,pl330-periph-burst;
367 clocks = <&cru ACLK_BUS>;
368 clock-names = "apb_pclk";
369 #dma-cells = <1>;
370 };
371
372 dmac1: dmac@fe550000 {
373 compatible = "arm,pl330", "arm,primecell";
374 reg = <0x0 0xfe550000 0x0 0x4000>;
375 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377 arm,pl330-periph-burst;
378 clocks = <&cru ACLK_BUS>;
379 clock-names = "apb_pclk";
380 #dma-cells = <1>;
381 };
382
383 i2c1: i2c@fe5a0000 {
384 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
385 reg = <0x0 0xfe5a0000 0x0 0x1000>;
386 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
388 clock-names = "i2c", "pclk";
389 pinctrl-0 = <&i2c1_xfer>;
390 pinctrl-names = "default";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 status = "disabled";
394 };
395
396 i2c2: i2c@fe5b0000 {
397 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
398 reg = <0x0 0xfe5b0000 0x0 0x1000>;
399 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
401 clock-names = "i2c", "pclk";
402 pinctrl-0 = <&i2c2m0_xfer>;
403 pinctrl-names = "default";
404 #address-cells = <1>;
405 #size-cells = <0>;
406 status = "disabled";
407 };
408
409 i2c3: i2c@fe5c0000 {
410 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
411 reg = <0x0 0xfe5c0000 0x0 0x1000>;
412 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
414 clock-names = "i2c", "pclk";
415 pinctrl-0 = <&i2c3m0_xfer>;
416 pinctrl-names = "default";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 status = "disabled";
420 };
421
422 i2c4: i2c@fe5d0000 {
423 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
424 reg = <0x0 0xfe5d0000 0x0 0x1000>;
425 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
427 clock-names = "i2c", "pclk";
428 pinctrl-0 = <&i2c4m0_xfer>;
429 pinctrl-names = "default";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 status = "disabled";
433 };
434
435 i2c5: i2c@fe5e0000 {
436 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
437 reg = <0x0 0xfe5e0000 0x0 0x1000>;
438 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
440 clock-names = "i2c", "pclk";
441 pinctrl-0 = <&i2c5m0_xfer>;
442 pinctrl-names = "default";
443 #address-cells = <1>;
444 #size-cells = <0>;
445 status = "disabled";
446 };
447
448 wdt: watchdog@fe600000 {
449 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
450 reg = <0x0 0xfe600000 0x0 0x100>;
451 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
453 clock-names = "tclk", "pclk";
454 };
455
456 uart1: serial@fe650000 {
457 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
458 reg = <0x0 0xfe650000 0x0 0x100>;
459 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
461 clock-names = "baudclk", "apb_pclk";
462 dmas = <&dmac0 2>, <&dmac0 3>;
463 pinctrl-0 = <&uart1m0_xfer>;
464 pinctrl-names = "default";
465 reg-io-width = <4>;
466 reg-shift = <2>;
467 status = "disabled";
468 };
469
470 uart2: serial@fe660000 {
471 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
472 reg = <0x0 0xfe660000 0x0 0x100>;
473 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
475 clock-names = "baudclk", "apb_pclk";
476 dmas = <&dmac0 4>, <&dmac0 5>;
477 pinctrl-0 = <&uart2m0_xfer>;
478 pinctrl-names = "default";
479 reg-io-width = <4>;
480 reg-shift = <2>;
481 status = "disabled";
482 };
483
484 uart3: serial@fe670000 {
485 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
486 reg = <0x0 0xfe670000 0x0 0x100>;
487 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
489 clock-names = "baudclk", "apb_pclk";
490 dmas = <&dmac0 6>, <&dmac0 7>;
491 pinctrl-0 = <&uart3m0_xfer>;
492 pinctrl-names = "default";
493 reg-io-width = <4>;
494 reg-shift = <2>;
495 status = "disabled";
496 };
497
498 uart4: serial@fe680000 {
499 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
500 reg = <0x0 0xfe680000 0x0 0x100>;
501 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
503 clock-names = "baudclk", "apb_pclk";
504 dmas = <&dmac0 8>, <&dmac0 9>;
505 pinctrl-0 = <&uart4m0_xfer>;
506 pinctrl-names = "default";
507 reg-io-width = <4>;
508 reg-shift = <2>;
509 status = "disabled";
510 };
511
512 uart5: serial@fe690000 {
513 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
514 reg = <0x0 0xfe690000 0x0 0x100>;
515 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
517 clock-names = "baudclk", "apb_pclk";
518 dmas = <&dmac0 10>, <&dmac0 11>;
519 pinctrl-0 = <&uart5m0_xfer>;
520 pinctrl-names = "default";
521 reg-io-width = <4>;
522 reg-shift = <2>;
523 status = "disabled";
524 };
525
526 uart6: serial@fe6a0000 {
527 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
528 reg = <0x0 0xfe6a0000 0x0 0x100>;
529 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
531 clock-names = "baudclk", "apb_pclk";
532 dmas = <&dmac0 12>, <&dmac0 13>;
533 pinctrl-0 = <&uart6m0_xfer>;
534 pinctrl-names = "default";
535 reg-io-width = <4>;
536 reg-shift = <2>;
537 status = "disabled";
538 };
539
540 uart7: serial@fe6b0000 {
541 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
542 reg = <0x0 0xfe6b0000 0x0 0x100>;
543 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
545 clock-names = "baudclk", "apb_pclk";
546 dmas = <&dmac0 14>, <&dmac0 15>;
547 pinctrl-0 = <&uart7m0_xfer>;
548 pinctrl-names = "default";
549 reg-io-width = <4>;
550 reg-shift = <2>;
551 status = "disabled";
552 };
553
554 uart8: serial@fe6c0000 {
555 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
556 reg = <0x0 0xfe6c0000 0x0 0x100>;
557 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
559 clock-names = "baudclk", "apb_pclk";
560 dmas = <&dmac0 16>, <&dmac0 17>;
561 pinctrl-0 = <&uart8m0_xfer>;
562 pinctrl-names = "default";
563 reg-io-width = <4>;
564 reg-shift = <2>;
565 status = "disabled";
566 };
567
568 uart9: serial@fe6d0000 {
569 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
570 reg = <0x0 0xfe6d0000 0x0 0x100>;
571 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
573 clock-names = "baudclk", "apb_pclk";
574 dmas = <&dmac0 18>, <&dmac0 19>;
575 pinctrl-0 = <&uart9m0_xfer>;
576 pinctrl-names = "default";
577 reg-io-width = <4>;
578 reg-shift = <2>;
579 status = "disabled";
580 };
581
582 pwm4: pwm@fe6e0000 {
583 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
584 reg = <0x0 0xfe6e0000 0x0 0x10>;
585 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
586 clock-names = "pwm", "pclk";
587 pinctrl-0 = <&pwm4_pins>;
588 pinctrl-names = "active";
589 #pwm-cells = <3>;
590 status = "disabled";
591 };
592
593 pwm5: pwm@fe6e0010 {
594 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
595 reg = <0x0 0xfe6e0010 0x0 0x10>;
596 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
597 clock-names = "pwm", "pclk";
598 pinctrl-0 = <&pwm5_pins>;
599 pinctrl-names = "active";
600 #pwm-cells = <3>;
601 status = "disabled";
602 };
603
604 pwm6: pwm@fe6e0020 {
605 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
606 reg = <0x0 0xfe6e0020 0x0 0x10>;
607 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
608 clock-names = "pwm", "pclk";
609 pinctrl-0 = <&pwm6_pins>;
610 pinctrl-names = "active";
611 #pwm-cells = <3>;
612 status = "disabled";
613 };
614
615 pwm7: pwm@fe6e0030 {
616 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
617 reg = <0x0 0xfe6e0030 0x0 0x10>;
618 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
619 clock-names = "pwm", "pclk";
620 pinctrl-0 = <&pwm7_pins>;
621 pinctrl-names = "active";
622 #pwm-cells = <3>;
623 status = "disabled";
624 };
625
626 pwm8: pwm@fe6f0000 {
627 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
628 reg = <0x0 0xfe6f0000 0x0 0x10>;
629 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
630 clock-names = "pwm", "pclk";
631 pinctrl-0 = <&pwm8m0_pins>;
632 pinctrl-names = "active";
633 #pwm-cells = <3>;
634 status = "disabled";
635 };
636
637 pwm9: pwm@fe6f0010 {
638 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
639 reg = <0x0 0xfe6f0010 0x0 0x10>;
640 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
641 clock-names = "pwm", "pclk";
642 pinctrl-0 = <&pwm9m0_pins>;
643 pinctrl-names = "active";
644 #pwm-cells = <3>;
645 status = "disabled";
646 };
647
648 pwm10: pwm@fe6f0020 {
649 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
650 reg = <0x0 0xfe6f0020 0x0 0x10>;
651 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
652 clock-names = "pwm", "pclk";
653 pinctrl-0 = <&pwm10m0_pins>;
654 pinctrl-names = "active";
655 #pwm-cells = <3>;
656 status = "disabled";
657 };
658
659 pwm11: pwm@fe6f0030 {
660 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
661 reg = <0x0 0xfe6f0030 0x0 0x10>;
662 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
663 clock-names = "pwm", "pclk";
664 pinctrl-0 = <&pwm11m0_pins>;
665 pinctrl-names = "active";
666 #pwm-cells = <3>;
667 status = "disabled";
668 };
669
670 pwm12: pwm@fe700000 {
671 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
672 reg = <0x0 0xfe700000 0x0 0x10>;
673 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
674 clock-names = "pwm", "pclk";
675 pinctrl-0 = <&pwm12m0_pins>;
676 pinctrl-names = "active";
677 #pwm-cells = <3>;
678 status = "disabled";
679 };
680
681 pwm13: pwm@fe700010 {
682 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
683 reg = <0x0 0xfe700010 0x0 0x10>;
684 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
685 clock-names = "pwm", "pclk";
686 pinctrl-0 = <&pwm13m0_pins>;
687 pinctrl-names = "active";
688 #pwm-cells = <3>;
689 status = "disabled";
690 };
691
692 pwm14: pwm@fe700020 {
693 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
694 reg = <0x0 0xfe700020 0x0 0x10>;
695 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
696 clock-names = "pwm", "pclk";
697 pinctrl-0 = <&pwm14m0_pins>;
698 pinctrl-names = "active";
699 #pwm-cells = <3>;
700 status = "disabled";
701 };
702
703 pwm15: pwm@fe700030 {
704 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
705 reg = <0x0 0xfe700030 0x0 0x10>;
706 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
707 clock-names = "pwm", "pclk";
708 pinctrl-0 = <&pwm15m0_pins>;
709 pinctrl-names = "active";
710 #pwm-cells = <3>;
711 status = "disabled";
712 };
713
714 pinctrl: pinctrl {
715 compatible = "rockchip,rk3568-pinctrl";
716 rockchip,grf = <&grf>;
717 rockchip,pmu = <&pmugrf>;
718 #address-cells = <2>;
719 #size-cells = <2>;
720 ranges;
721
722 gpio0: gpio@fdd60000 {
723 compatible = "rockchip,gpio-bank";
724 reg = <0x0 0xfdd60000 0x0 0x100>;
725 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
727 gpio-controller;
728 #gpio-cells = <2>;
729 interrupt-controller;
730 #interrupt-cells = <2>;
731 };
732
733 gpio1: gpio@fe740000 {
734 compatible = "rockchip,gpio-bank";
735 reg = <0x0 0xfe740000 0x0 0x100>;
736 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
738 gpio-controller;
739 #gpio-cells = <2>;
740 interrupt-controller;
741 #interrupt-cells = <2>;
742 };
743
744 gpio2: gpio@fe750000 {
745 compatible = "rockchip,gpio-bank";
746 reg = <0x0 0xfe750000 0x0 0x100>;
747 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
749 gpio-controller;
750 #gpio-cells = <2>;
751 interrupt-controller;
752 #interrupt-cells = <2>;
753 };
754
755 gpio3: gpio@fe760000 {
756 compatible = "rockchip,gpio-bank";
757 reg = <0x0 0xfe760000 0x0 0x100>;
758 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
760 gpio-controller;
761 #gpio-cells = <2>;
762 interrupt-controller;
763 #interrupt-cells = <2>;
764 };
765
766 gpio4: gpio@fe770000 {
767 compatible = "rockchip,gpio-bank";
768 reg = <0x0 0xfe770000 0x0 0x100>;
769 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
771 gpio-controller;
772 #gpio-cells = <2>;
773 interrupt-controller;
774 #interrupt-cells = <2>;
775 };
776 };
777};
778
779#include "rk3568-pinctrl.dtsi"