Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010,2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _PINMUX_H_ |
| 9 | #define _PINMUX_H_ |
| 10 | |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 11 | /* |
| 12 | * Pin groups which we adjust. There are three basic attributes of each pin |
| 13 | * group which use this enum: |
| 14 | * |
| 15 | * - function |
| 16 | * - pullup / pulldown |
| 17 | * - tristate or normal |
| 18 | */ |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 19 | enum pmux_pingrp { |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 20 | /* APB_MISC_PP_TRISTATE_REG_A_0 */ |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 21 | PINGRP_ATA, |
| 22 | PINGRP_ATB, |
| 23 | PINGRP_ATC, |
| 24 | PINGRP_ATD, |
| 25 | PINGRP_CDEV1, |
| 26 | PINGRP_CDEV2, |
| 27 | PINGRP_CSUS, |
| 28 | PINGRP_DAP1, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 29 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 30 | PINGRP_DAP2, |
| 31 | PINGRP_DAP3, |
| 32 | PINGRP_DAP4, |
| 33 | PINGRP_DTA, |
| 34 | PINGRP_DTB, |
| 35 | PINGRP_DTC, |
| 36 | PINGRP_DTD, |
| 37 | PINGRP_DTE, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 38 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 39 | PINGRP_GPU, |
| 40 | PINGRP_GPV, |
| 41 | PINGRP_I2CP, |
| 42 | PINGRP_IRTX, |
| 43 | PINGRP_IRRX, |
| 44 | PINGRP_KBCB, |
| 45 | PINGRP_KBCA, |
| 46 | PINGRP_PMC, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 47 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 48 | PINGRP_PTA, |
| 49 | PINGRP_RM, |
| 50 | PINGRP_KBCE, |
| 51 | PINGRP_KBCF, |
| 52 | PINGRP_GMA, |
| 53 | PINGRP_GMC, |
Lucas Stach | 2249fb6 | 2012-05-16 08:21:01 +0000 | [diff] [blame] | 54 | PINGRP_SDIO1, |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 55 | PINGRP_OWC, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 56 | |
| 57 | /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 58 | PINGRP_GME, |
| 59 | PINGRP_SDC, |
| 60 | PINGRP_SDD, |
| 61 | PINGRP_RESERVED0, |
| 62 | PINGRP_SLXA, |
| 63 | PINGRP_SLXC, |
| 64 | PINGRP_SLXD, |
| 65 | PINGRP_SLXK, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 66 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 67 | PINGRP_SPDI, |
| 68 | PINGRP_SPDO, |
| 69 | PINGRP_SPIA, |
| 70 | PINGRP_SPIB, |
| 71 | PINGRP_SPIC, |
| 72 | PINGRP_SPID, |
| 73 | PINGRP_SPIE, |
| 74 | PINGRP_SPIF, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 75 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 76 | PINGRP_SPIG, |
| 77 | PINGRP_SPIH, |
| 78 | PINGRP_UAA, |
| 79 | PINGRP_UAB, |
| 80 | PINGRP_UAC, |
| 81 | PINGRP_UAD, |
| 82 | PINGRP_UCA, |
| 83 | PINGRP_UCB, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 84 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 85 | PINGRP_RESERVED1, |
| 86 | PINGRP_ATE, |
| 87 | PINGRP_KBCC, |
| 88 | PINGRP_RESERVED2, |
| 89 | PINGRP_RESERVED3, |
| 90 | PINGRP_GMB, |
| 91 | PINGRP_GMD, |
| 92 | PINGRP_DDC, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 93 | |
| 94 | /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 95 | PINGRP_LD0, |
| 96 | PINGRP_LD1, |
| 97 | PINGRP_LD2, |
| 98 | PINGRP_LD3, |
| 99 | PINGRP_LD4, |
| 100 | PINGRP_LD5, |
| 101 | PINGRP_LD6, |
| 102 | PINGRP_LD7, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 103 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 104 | PINGRP_LD8, |
| 105 | PINGRP_LD9, |
| 106 | PINGRP_LD10, |
| 107 | PINGRP_LD11, |
| 108 | PINGRP_LD12, |
| 109 | PINGRP_LD13, |
| 110 | PINGRP_LD14, |
| 111 | PINGRP_LD15, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 112 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 113 | PINGRP_LD16, |
| 114 | PINGRP_LD17, |
| 115 | PINGRP_LHP0, |
| 116 | PINGRP_LHP1, |
| 117 | PINGRP_LHP2, |
| 118 | PINGRP_LVP0, |
| 119 | PINGRP_LVP1, |
| 120 | PINGRP_HDINT, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 121 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 122 | PINGRP_LM0, |
| 123 | PINGRP_LM1, |
| 124 | PINGRP_LVS, |
| 125 | PINGRP_LSC0, |
| 126 | PINGRP_LSC1, |
| 127 | PINGRP_LSCK, |
| 128 | PINGRP_LDC, |
| 129 | PINGRP_LCSN, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 130 | |
| 131 | /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 132 | PINGRP_LSPI, |
| 133 | PINGRP_LSDA, |
| 134 | PINGRP_LSDI, |
| 135 | PINGRP_LPW0, |
| 136 | PINGRP_LPW1, |
| 137 | PINGRP_LPW2, |
| 138 | PINGRP_LDI, |
| 139 | PINGRP_LHS, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 140 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 141 | PINGRP_LPP, |
| 142 | PINGRP_RESERVED4, |
| 143 | PINGRP_KBCD, |
| 144 | PINGRP_GPU7, |
| 145 | PINGRP_DTF, |
| 146 | PINGRP_UDA, |
| 147 | PINGRP_CRTP, |
| 148 | PINGRP_SDB, |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 149 | |
| 150 | /* these pin groups only have pullup and pull down control */ |
| 151 | PINGRP_FIRST_NO_MUX, |
| 152 | PINGRP_CK32 = PINGRP_FIRST_NO_MUX, |
| 153 | PINGRP_DDRC, |
| 154 | PINGRP_PMCA, |
| 155 | PINGRP_PMCB, |
| 156 | PINGRP_PMCC, |
| 157 | PINGRP_PMCD, |
| 158 | PINGRP_PMCE, |
| 159 | PINGRP_XM2C, |
| 160 | PINGRP_XM2D, |
| 161 | |
| 162 | PINGRP_COUNT, |
| 163 | }; |
| 164 | |
| 165 | /* |
| 166 | * Functions which can be assigned to each of the pin groups. The values here |
| 167 | * bear no relation to the values programmed into pinmux registers and are |
| 168 | * purely a convenience. The translation is done through a table search. |
| 169 | */ |
| 170 | enum pmux_func { |
| 171 | PMUX_FUNC_AHB_CLK, |
| 172 | PMUX_FUNC_APB_CLK, |
| 173 | PMUX_FUNC_AUDIO_SYNC, |
| 174 | PMUX_FUNC_CRT, |
| 175 | PMUX_FUNC_DAP1, |
| 176 | PMUX_FUNC_DAP2, |
| 177 | PMUX_FUNC_DAP3, |
| 178 | PMUX_FUNC_DAP4, |
| 179 | PMUX_FUNC_DAP5, |
| 180 | PMUX_FUNC_DISPA, |
| 181 | PMUX_FUNC_DISPB, |
| 182 | PMUX_FUNC_EMC_TEST0_DLL, |
| 183 | PMUX_FUNC_EMC_TEST1_DLL, |
| 184 | PMUX_FUNC_GMI, |
| 185 | PMUX_FUNC_GMI_INT, |
| 186 | PMUX_FUNC_HDMI, |
| 187 | PMUX_FUNC_I2C, |
| 188 | PMUX_FUNC_I2C2, |
| 189 | PMUX_FUNC_I2C3, |
| 190 | PMUX_FUNC_IDE, |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 191 | PMUX_FUNC_KBC, |
| 192 | PMUX_FUNC_MIO, |
| 193 | PMUX_FUNC_MIPI_HS, |
| 194 | PMUX_FUNC_NAND, |
| 195 | PMUX_FUNC_OSC, |
| 196 | PMUX_FUNC_OWR, |
| 197 | PMUX_FUNC_PCIE, |
| 198 | PMUX_FUNC_PLLA_OUT, |
| 199 | PMUX_FUNC_PLLC_OUT1, |
| 200 | PMUX_FUNC_PLLM_OUT1, |
| 201 | PMUX_FUNC_PLLP_OUT2, |
| 202 | PMUX_FUNC_PLLP_OUT3, |
| 203 | PMUX_FUNC_PLLP_OUT4, |
| 204 | PMUX_FUNC_PWM, |
| 205 | PMUX_FUNC_PWR_INTR, |
| 206 | PMUX_FUNC_PWR_ON, |
| 207 | PMUX_FUNC_RTCK, |
| 208 | PMUX_FUNC_SDIO1, |
| 209 | PMUX_FUNC_SDIO2, |
| 210 | PMUX_FUNC_SDIO3, |
| 211 | PMUX_FUNC_SDIO4, |
| 212 | PMUX_FUNC_SFLASH, |
| 213 | PMUX_FUNC_SPDIF, |
| 214 | PMUX_FUNC_SPI1, |
| 215 | PMUX_FUNC_SPI2, |
| 216 | PMUX_FUNC_SPI2_ALT, |
| 217 | PMUX_FUNC_SPI3, |
| 218 | PMUX_FUNC_SPI4, |
| 219 | PMUX_FUNC_TRACE, |
| 220 | PMUX_FUNC_TWC, |
| 221 | PMUX_FUNC_UARTA, |
| 222 | PMUX_FUNC_UARTB, |
| 223 | PMUX_FUNC_UARTC, |
| 224 | PMUX_FUNC_UARTD, |
| 225 | PMUX_FUNC_UARTE, |
| 226 | PMUX_FUNC_ULPI, |
| 227 | PMUX_FUNC_VI, |
| 228 | PMUX_FUNC_VI_SENSOR_CLK, |
| 229 | PMUX_FUNC_XIO, |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 230 | |
| 231 | /* These don't have a name, but can be used in the table */ |
| 232 | PMUX_FUNC_RSVD1, |
| 233 | PMUX_FUNC_RSVD2, |
| 234 | PMUX_FUNC_RSVD3, |
| 235 | PMUX_FUNC_RSVD4, |
| 236 | PMUX_FUNC_RSVD, /* Not valid and should not be used */ |
| 237 | |
| 238 | PMUX_FUNC_COUNT, |
| 239 | |
| 240 | PMUX_FUNC_NONE = -1, |
| 241 | }; |
| 242 | |
| 243 | /* return 1 if a pmux_func is in range */ |
| 244 | #define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \ |
| 245 | (func) != PMUX_FUNC_RSVD) |
| 246 | |
| 247 | /* The pullup/pulldown state of a pin group */ |
| 248 | enum pmux_pull { |
| 249 | PMUX_PULL_NORMAL = 0, |
| 250 | PMUX_PULL_DOWN, |
| 251 | PMUX_PULL_UP, |
| 252 | }; |
| 253 | |
| 254 | /* Defines whether a pin group is tristated or in normal operation */ |
| 255 | enum pmux_tristate { |
| 256 | PMUX_TRI_NORMAL = 0, |
| 257 | PMUX_TRI_TRISTATE = 1, |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 258 | }; |
| 259 | |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 260 | enum { |
| 261 | PMUX_TRISTATE_REGS = 4, |
| 262 | PMUX_MUX_REGS = 7, |
| 263 | PMUX_PULL_REGS = 5, |
| 264 | }; |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 265 | |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 266 | /* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */ |
| 267 | struct pmux_tri_ctlr { |
| 268 | uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ |
| 269 | uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 270 | uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 271 | uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ |
| 272 | uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 273 | uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */ |
| 274 | uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 275 | |
| 276 | uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ |
| 277 | |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 278 | uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */ |
| 279 | uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */ |
| 280 | uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */ |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 281 | }; |
| 282 | |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 283 | /* |
| 284 | * This defines the configuration for a pin, including the function assigned, |
| 285 | * pull up/down settings and tristate settings. Having set up one of these |
| 286 | * you can call pinmux_config_pingroup() to configure a pin in one step. Also |
| 287 | * available is pinmux_config_table() to configure a list of pins. |
| 288 | */ |
| 289 | struct pingroup_config { |
| 290 | enum pmux_pingrp pingroup; /* pin group PINGRP_... */ |
| 291 | enum pmux_func func; /* function to assign FUNC_... */ |
| 292 | enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ |
| 293 | enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ |
| 294 | }; |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 295 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 296 | /* Set a pin group to tristate */ |
| 297 | void pinmux_tristate_enable(enum pmux_pingrp pin); |
Simon Glass | fa516f6 | 2011-08-30 06:23:14 +0000 | [diff] [blame] | 298 | |
Simon Glass | 80608ed | 2011-09-21 12:40:05 +0000 | [diff] [blame] | 299 | /* Set a pin group to normal (non tristate) */ |
| 300 | void pinmux_tristate_disable(enum pmux_pingrp pin); |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 301 | |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 302 | /* Set the pull up/down feature for a pin group */ |
| 303 | void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); |
| 304 | |
| 305 | /* Set the mux function for a pin group */ |
| 306 | void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); |
| 307 | |
| 308 | /* Set the complete configuration for a pin group */ |
Simon Glass | 20b2acb | 2012-10-17 13:24:45 +0000 | [diff] [blame] | 309 | void pinmux_config_pingroup(const struct pingroup_config *config); |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 310 | |
| 311 | void pinmux_set_tristate(enum pmux_pingrp pin, int enable); |
| 312 | |
| 313 | /** |
| 314 | * Configuure a list of pin groups |
| 315 | * |
| 316 | * @param config List of config items |
| 317 | * @param len Number of config items in list |
| 318 | */ |
Simon Glass | 20b2acb | 2012-10-17 13:24:45 +0000 | [diff] [blame] | 319 | void pinmux_config_table(const struct pingroup_config *config, int len); |
Simon Glass | b70bbf1 | 2011-09-21 12:40:06 +0000 | [diff] [blame] | 320 | |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 321 | #endif /* PINMUX_H */ |