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git01.mediatek.com / filogic / uboot / 845226e8a13c84cdb0227ad3f0fd9d69faa0dd9f / . / drivers / net / fm / memac_phy.c
blob: 2f4bc11a6c294e6b1912e5ef12970f26d00cdb06 [file] [log] [blame]
Roy Zangbafd8032012-10-08 07:44:21 +0000[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Andy Fleming <afleming@freescale.com>
4 * Roy Zang <tie-fei.zang@freescale.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Roy Zangbafd8032012-10-08 07:44:21 +0000[diff] [blame]7 * Some part is taken from tsec.c
8 */
9#include <common.h>
10#include <miiphy.h>
11#include <phy.h>
12#include <asm/io.h>
13#include <asm/fsl_memac.h>
14#include <fm_eth.h>
15
16/*
17 * Write value to the PHY for this device to the register at regnum, waiting
18 * until the write is done before it returns. All PHY configuration has to be
19 * done through the TSEC1 MIIM regs
20 */
21int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
22 int regnum, u16 value)
23{
24 u32 mdio_ctl;
25 struct memac_mdio_controller *regs = bus->priv;
26 u32 c45 = 1; /* Default to 10G interface */
27
28 if (dev_addr == MDIO_DEVAD_NONE) {
29 c45 = 0; /* clause 22 */
30 dev_addr = regnum & 0x1f;
31 clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
32 } else {
33 setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
34 setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
35 }
36
37 /* Wait till the bus is free */
38 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
39 ;
40
41 /* Set the port and dev addr */
42 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
43 out_be32(&regs->mdio_ctl, mdio_ctl);
44
45 /* Set the register address */
46 if (c45)
47 out_be32(&regs->mdio_addr, regnum & 0xffff);
48
49 /* Wait till the bus is free */
50 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
51 ;
52
53 /* Write the value to the register */
54 out_be32(&regs->mdio_data, MDIO_DATA(value));
55
56 /* Wait till the MDIO write is complete */
57 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
58 ;
59
60 return 0;
61}
62
63/*
64 * Reads from register regnum in the PHY for device dev, returning the value.
65 * Clears miimcom first. All PHY configuration has to be done through the
66 * TSEC1 MIIM regs
67 */
68int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
69 int regnum)
70{
71 u32 mdio_ctl;
72 struct memac_mdio_controller *regs = bus->priv;
73 u32 c45 = 1;
74
75 if (dev_addr == MDIO_DEVAD_NONE) {
76 c45 = 0; /* clause 22 */
77 dev_addr = regnum & 0x1f;
78 clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
79 } else {
80 setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
81 setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
82 }
83
84 /* Wait till the bus is free */
85 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
86 ;
87
88 /* Set the Port and Device Addrs */
89 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
90 out_be32(&regs->mdio_ctl, mdio_ctl);
91
92 /* Set the register address */
93 if (c45)
94 out_be32(&regs->mdio_addr, regnum & 0xffff);
95
96 /* Wait till the bus is free */
97 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
98 ;
99
100 /* Initiate the read */
101 mdio_ctl |= MDIO_CTL_READ;
102 out_be32(&regs->mdio_ctl, mdio_ctl);
103
104 /* Wait till the MDIO write is complete */
105 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
106 ;
107
108 /* Return all Fs if nothing was there */
109 if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
110 return 0xffff;
111
112 return in_be32(&regs->mdio_data) & 0xffff;
113}
114
115int memac_mdio_reset(struct mii_dev *bus)
116{
117 return 0;
118}
119
120int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
121{
122 struct mii_dev *bus = mdio_alloc();
123
124 if (!bus) {
125 printf("Failed to allocate FM TGEC MDIO bus\n");
126 return -1;
127 }
128
129 bus->read = memac_mdio_read;
130 bus->write = memac_mdio_write;
131 bus->reset = memac_mdio_reset;
132 sprintf(bus->name, info->name);
133
134 bus->priv = info->regs;
135
Priyanka Jain845226e2014-04-08 10:55:49 +0530[diff] [blame^]136 /*
137 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
138 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
139 * (much higher than 2.5MHz), violating the IEEE specs.
140 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
141 * is zero, so MDIO clock is disabled.
142 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
143 * be properly initialized.
144 */
145 setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
146 MDIO_STAT_CLKDIV(258));
147
Roy Zangbafd8032012-10-08 07:44:21 +0000[diff] [blame]148 return mdio_register(bus);
149}