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git01.mediatek.com / filogic / uboot / 81d5b90e6e96649265d370b002091398e20472a0 / . / drivers / net / davinci_emac.h
blob: 37c841ca84a129e909b420af693e17bb70c9ba66 [file] [log] [blame]
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3 *
4 * Based on: mach-davinci/emac_defs.h
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _DAVINCI_EMAC_H_
23#define _DAVINCI_EMAC_H_
24/* Ethernet Min/Max packet size */
25#define EMAC_MIN_ETHERNET_PKT_SIZE 60
26#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
Ilya Yanokff672762011-11-28 06:37:33 +0000[diff] [blame]27/* Buffer size (should be aligned on 32 byte and cache line) */
28#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
29 ARCH_DMA_MINALIGN)
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]30
31/* Number of RX packet buffers
32 * NOTE: Only 1 buffer supported as of now
33 */
34#define EMAC_MAX_RX_BUFFERS 10
35
36
37/***********************************************
38 ******** Internally used macros ***************
39 ***********************************************/
40
41#define EMAC_CH_TX 1
42#define EMAC_CH_RX 0
43
44/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
45 * reserve space for 64 descriptors max
46 */
47#define EMAC_RX_DESC_BASE 0x0
48#define EMAC_TX_DESC_BASE 0x1000
49
50/* EMAC Teardown value */
51#define EMAC_TEARDOWN_VALUE 0xfffffffc
52
53/* MII Status Register */
54#define MII_STATUS_REG 1
55
56/* Number of statistics registers */
57#define EMAC_NUM_STATS 36
58
59
60/* EMAC Descriptor */
61typedef volatile struct _emac_desc
62{
63 u_int32_t next; /* Pointer to next descriptor
64 in chain */
65 u_int8_t *buffer; /* Pointer to data buffer */
66 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
67 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
68} emac_desc;
69
70/* CPPI bit positions */
71#define EMAC_CPPI_SOP_BIT (0x80000000)
72#define EMAC_CPPI_EOP_BIT (0x40000000)
73#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
74#define EMAC_CPPI_EOQ_BIT (0x10000000)
75#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
76#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
77
78#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
79
80#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
81#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
82#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
83#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
84#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
85
86#define EMAC_MAC_ADDR_MATCH (1 << 19)
87#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
88
89#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
90#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
91
92
93#define MDIO_CONTROL_IDLE (0x80000000)
94#define MDIO_CONTROL_ENABLE (0x40000000)
95#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
96#define MDIO_CONTROL_FAULT (0x80000)
97#define MDIO_USERACCESS0_GO (0x80000000)
98#define MDIO_USERACCESS0_WRITE_READ (0x0)
99#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
100#define MDIO_USERACCESS0_ACK (0x20000000)
101
102/* Ethernet MAC Registers Structure */
103typedef struct {
104 dv_reg TXIDVER;
105 dv_reg TXCONTROL;
106 dv_reg TXTEARDOWN;
107 u_int8_t RSVD0[4];
108 dv_reg RXIDVER;
109 dv_reg RXCONTROL;
110 dv_reg RXTEARDOWN;
111 u_int8_t RSVD1[100];
112 dv_reg TXINTSTATRAW;
113 dv_reg TXINTSTATMASKED;
114 dv_reg TXINTMASKSET;
115 dv_reg TXINTMASKCLEAR;
116 dv_reg MACINVECTOR;
117 u_int8_t RSVD2[12];
118 dv_reg RXINTSTATRAW;
119 dv_reg RXINTSTATMASKED;
120 dv_reg RXINTMASKSET;
121 dv_reg RXINTMASKCLEAR;
122 dv_reg MACINTSTATRAW;
123 dv_reg MACINTSTATMASKED;
124 dv_reg MACINTMASKSET;
125 dv_reg MACINTMASKCLEAR;
126 u_int8_t RSVD3[64];
127 dv_reg RXMBPENABLE;
128 dv_reg RXUNICASTSET;
129 dv_reg RXUNICASTCLEAR;
130 dv_reg RXMAXLEN;
131 dv_reg RXBUFFEROFFSET;
132 dv_reg RXFILTERLOWTHRESH;
133 u_int8_t RSVD4[8];
134 dv_reg RX0FLOWTHRESH;
135 dv_reg RX1FLOWTHRESH;
136 dv_reg RX2FLOWTHRESH;
137 dv_reg RX3FLOWTHRESH;
138 dv_reg RX4FLOWTHRESH;
139 dv_reg RX5FLOWTHRESH;
140 dv_reg RX6FLOWTHRESH;
141 dv_reg RX7FLOWTHRESH;
142 dv_reg RX0FREEBUFFER;
143 dv_reg RX1FREEBUFFER;
144 dv_reg RX2FREEBUFFER;
145 dv_reg RX3FREEBUFFER;
146 dv_reg RX4FREEBUFFER;
147 dv_reg RX5FREEBUFFER;
148 dv_reg RX6FREEBUFFER;
149 dv_reg RX7FREEBUFFER;
150 dv_reg MACCONTROL;
151 dv_reg MACSTATUS;
152 dv_reg EMCONTROL;
153 dv_reg FIFOCONTROL;
154 dv_reg MACCONFIG;
155 dv_reg SOFTRESET;
156 u_int8_t RSVD5[88];
157 dv_reg MACSRCADDRLO;
158 dv_reg MACSRCADDRHI;
159 dv_reg MACHASH1;
160 dv_reg MACHASH2;
161 dv_reg BOFFTEST;
162 dv_reg TPACETEST;
163 dv_reg RXPAUSE;
164 dv_reg TXPAUSE;
165 u_int8_t RSVD6[16];
166 dv_reg RXGOODFRAMES;
167 dv_reg RXBCASTFRAMES;
168 dv_reg RXMCASTFRAMES;
169 dv_reg RXPAUSEFRAMES;
170 dv_reg RXCRCERRORS;
171 dv_reg RXALIGNCODEERRORS;
172 dv_reg RXOVERSIZED;
173 dv_reg RXJABBER;
174 dv_reg RXUNDERSIZED;
175 dv_reg RXFRAGMENTS;
176 dv_reg RXFILTERED;
177 dv_reg RXQOSFILTERED;
178 dv_reg RXOCTETS;
179 dv_reg TXGOODFRAMES;
180 dv_reg TXBCASTFRAMES;
181 dv_reg TXMCASTFRAMES;
182 dv_reg TXPAUSEFRAMES;
183 dv_reg TXDEFERRED;
184 dv_reg TXCOLLISION;
185 dv_reg TXSINGLECOLL;
186 dv_reg TXMULTICOLL;
187 dv_reg TXEXCESSIVECOLL;
188 dv_reg TXLATECOLL;
189 dv_reg TXUNDERRUN;
190 dv_reg TXCARRIERSENSE;
191 dv_reg TXOCTETS;
192 dv_reg FRAME64;
193 dv_reg FRAME65T127;
194 dv_reg FRAME128T255;
195 dv_reg FRAME256T511;
196 dv_reg FRAME512T1023;
197 dv_reg FRAME1024TUP;
198 dv_reg NETOCTETS;
199 dv_reg RXSOFOVERRUNS;
200 dv_reg RXMOFOVERRUNS;
201 dv_reg RXDMAOVERRUNS;
202 u_int8_t RSVD7[624];
203 dv_reg MACADDRLO;
204 dv_reg MACADDRHI;
205 dv_reg MACINDEX;
206 u_int8_t RSVD8[244];
207 dv_reg TX0HDP;
208 dv_reg TX1HDP;
209 dv_reg TX2HDP;
210 dv_reg TX3HDP;
211 dv_reg TX4HDP;
212 dv_reg TX5HDP;
213 dv_reg TX6HDP;
214 dv_reg TX7HDP;
215 dv_reg RX0HDP;
216 dv_reg RX1HDP;
217 dv_reg RX2HDP;
218 dv_reg RX3HDP;
219 dv_reg RX4HDP;
220 dv_reg RX5HDP;
221 dv_reg RX6HDP;
222 dv_reg RX7HDP;
223 dv_reg TX0CP;
224 dv_reg TX1CP;
225 dv_reg TX2CP;
226 dv_reg TX3CP;
227 dv_reg TX4CP;
228 dv_reg TX5CP;
229 dv_reg TX6CP;
230 dv_reg TX7CP;
231 dv_reg RX0CP;
232 dv_reg RX1CP;
233 dv_reg RX2CP;
234 dv_reg RX3CP;
235 dv_reg RX4CP;
236 dv_reg RX5CP;
237 dv_reg RX6CP;
238 dv_reg RX7CP;
239} emac_regs;
240
241/* EMAC Wrapper Registers Structure */
242typedef struct {
243#ifdef DAVINCI_EMAC_VERSION2
244 dv_reg idver;
245 dv_reg softrst;
246 dv_reg emctrl;
247 dv_reg c0rxthreshen;
248 dv_reg c0rxen;
249 dv_reg c0txen;
250 dv_reg c0miscen;
251 dv_reg c1rxthreshen;
252 dv_reg c1rxen;
253 dv_reg c1txen;
254 dv_reg c1miscen;
255 dv_reg c2rxthreshen;
256 dv_reg c2rxen;
257 dv_reg c2txen;
258 dv_reg c2miscen;
259 dv_reg c0rxthreshstat;
260 dv_reg c0rxstat;
261 dv_reg c0txstat;
262 dv_reg c0miscstat;
263 dv_reg c1rxthreshstat;
264 dv_reg c1rxstat;
265 dv_reg c1txstat;
266 dv_reg c1miscstat;
267 dv_reg c2rxthreshstat;
268 dv_reg c2rxstat;
269 dv_reg c2txstat;
270 dv_reg c2miscstat;
271 dv_reg c0rximax;
272 dv_reg c0tximax;
273 dv_reg c1rximax;
274 dv_reg c1tximax;
275 dv_reg c2rximax;
276 dv_reg c2tximax;
277#else
278 u_int8_t RSVD0[4100];
279 dv_reg EWCTL;
280 dv_reg EWINTTCNT;
281#endif
282} ewrap_regs;
283
284/* EMAC MDIO Registers Structure */
285typedef struct {
286 dv_reg VERSION;
287 dv_reg CONTROL;
288 dv_reg ALIVE;
289 dv_reg LINK;
290 dv_reg LINKINTRAW;
291 dv_reg LINKINTMASKED;
292 u_int8_t RSVD0[8];
293 dv_reg USERINTRAW;
294 dv_reg USERINTMASKED;
295 dv_reg USERINTMASKSET;
296 dv_reg USERINTMASKCLEAR;
297 u_int8_t RSVD1[80];
298 dv_reg USERACCESS0;
299 dv_reg USERPHYSEL0;
300 dv_reg USERACCESS1;
301 dv_reg USERPHYSEL1;
302} mdio_regs;
303
304int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
305int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
306
307typedef struct {
308 char name[64];
309 int (*init)(int phy_addr);
310 int (*is_phy_connected)(int phy_addr);
311 int (*get_link_speed)(int phy_addr);
312 int (*auto_negotiate)(int phy_addr);
313} phy_t;
314
315#endif /* _DAVINCI_EMAC_H_ */