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git01.mediatek.com / filogic / uboot / 7f2cba463fc4488a3c24b422076683b0f6945177 / . / arch / arm / dts / rk3288-tinker-u-boot.dtsi
blob: 0cf1b696d1683c95024ba14de734e04c07ad9601 [file] [log] [blame]
Kever Yang0c518472019-07-01 11:49:11 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Rockchip Electronics Co., Ltd
4 */
5
6#include "rk3288-u-boot.dtsi"
7
Michael Trimarchifeb40d22019-11-15 22:07:23 +0100[diff] [blame]8&dmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]9 bootph-all;
Michael Trimarchifeb40d22019-11-15 22:07:23 +0100[diff] [blame]10 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
11 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
12 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
13 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
14 0x8 0x1f4>;
15 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
16 0x0 0xc3 0x6 0x2>;
17 rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
18};
19
Stefan Agner96da29c2020-09-04 16:11:08 +0200[diff] [blame]20&i2c2 {
21 m24c08@50 {
22 compatible = "at,24c08", "i2c-eeprom";
23 reg = <0x50>;
24 };
25};
26
Kever Yang0c518472019-07-01 11:49:11 +0800[diff] [blame]27&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-all;
Kever Yang0c518472019-07-01 11:49:11 +0800[diff] [blame]29};
30
31&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-all;
Kever Yang0c518472019-07-01 11:49:11 +0800[diff] [blame]33};
34
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]35&uart2_xfer {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-all;
Kever Yang0c518472019-07-01 11:49:11 +0800[diff] [blame]37};
38
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]39&sdmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Kever Yang0c518472019-07-01 11:49:11 +0800[diff] [blame]41};
42
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]43&gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Kever Yang0c518472019-07-01 11:49:11 +0800[diff] [blame]45};
46
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]47&vcc_sd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Kever Yang0c518472019-07-01 11:49:11 +0800[diff] [blame]49};
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]50
51&pcfg_pull_none_drv_8ma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]53};
54
55&pcfg_pull_up_drv_8ma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]57};
58
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]59&pcfg_pull_none {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]61};
62
63&pcfg_pull_up {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]65};
66
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]67&sdmmc_bus4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]69};
70
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]71&sdmmc_cd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]73};
74
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]75&sdmmc_clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]77};
78
79&sdmmc_cmd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]81};
82
83&sdmmc_pwr {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Kever Yang3804b762019-07-01 11:49:12 +0800[diff] [blame]85};