Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 |
| 3 | * Marvell Semiconductor <www.marvell.com> |
| 4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
| 5 | * |
| 6 | * (C) Copyright 2003 |
| 7 | * Ingo Assmus <ingo.assmus@keymile.com> |
| 8 | * |
| 9 | * based on - Driver for MV64360X ethernet ports |
| 10 | * Copyright (C) 2002 rabeeh@galileo.co.il |
| 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 28 | * MA 02110-1301 USA |
| 29 | */ |
| 30 | |
| 31 | #include <common.h> |
| 32 | #include <net.h> |
| 33 | #include <malloc.h> |
| 34 | #include <miiphy.h> |
Lei Wen | 298ae91 | 2011-10-18 20:11:42 +0530 | [diff] [blame] | 35 | #include <asm/io.h> |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 36 | #include <asm/errno.h> |
| 37 | #include <asm/types.h> |
Lei Wen | 298ae91 | 2011-10-18 20:11:42 +0530 | [diff] [blame] | 38 | #include <asm/system.h> |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 39 | #include <asm/byteorder.h> |
Anatolij Gustschin | c8b222e | 2011-10-29 10:09:22 +0000 | [diff] [blame] | 40 | #include <asm/arch/cpu.h> |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 41 | |
| 42 | #if defined(CONFIG_KIRKWOOD) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 43 | #include <asm/arch/kirkwood.h> |
Albert Aribaud | 8a99523 | 2010-07-12 22:24:29 +0200 | [diff] [blame] | 44 | #elif defined(CONFIG_ORION5X) |
| 45 | #include <asm/arch/orion5x.h> |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 46 | #endif |
| 47 | |
Albert Aribaud | 0d027d9 | 2010-07-12 22:24:27 +0200 | [diff] [blame] | 48 | #include "mvgbe.h" |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 49 | |
Albert Aribaud | a756407 | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 50 | DECLARE_GLOBAL_DATA_PTR; |
| 51 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 52 | #define MV_PHY_ADR_REQUEST 0xee |
| 53 | #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) |
Simon Kagstrom | ab9ca51 | 2009-08-20 10:12:28 +0200 | [diff] [blame] | 54 | |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 55 | /* |
| 56 | * smi_reg_read - miiphy_read callback function. |
| 57 | * |
| 58 | * Returns 16bit phy register value, or 0xffff on error |
| 59 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 60 | static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 61 | { |
| 62 | struct eth_device *dev = eth_get_dev_by_name(devname); |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 63 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 64 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 65 | u32 smi_reg; |
Simon Kagstrom | 4d0941c | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 66 | u32 timeout; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 67 | |
| 68 | /* Phyadr read request */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 69 | if (phy_adr == MV_PHY_ADR_REQUEST && |
| 70 | reg_ofs == MV_PHY_ADR_REQUEST) { |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 71 | /* */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 72 | *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 73 | return 0; |
| 74 | } |
| 75 | /* check parameters */ |
| 76 | if (phy_adr > PHYADR_MASK) { |
| 77 | printf("Err..(%s) Invalid PHY address %d\n", |
| 78 | __FUNCTION__, phy_adr); |
| 79 | return -EFAULT; |
| 80 | } |
| 81 | if (reg_ofs > PHYREG_MASK) { |
| 82 | printf("Err..(%s) Invalid register offset %d\n", |
| 83 | __FUNCTION__, reg_ofs); |
| 84 | return -EFAULT; |
| 85 | } |
| 86 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 87 | timeout = MVGBE_PHY_SMI_TIMEOUT; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 88 | /* wait till the SMI is not busy */ |
| 89 | do { |
| 90 | /* read smi register */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 91 | smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 92 | if (timeout-- == 0) { |
| 93 | printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); |
| 94 | return -EFAULT; |
| 95 | } |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 96 | } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 97 | |
| 98 | /* fill the phy address and regiser offset and read opcode */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 99 | smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) |
| 100 | | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS) |
| 101 | | MVGBE_PHY_SMI_OPCODE_READ; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 102 | |
| 103 | /* write the smi register */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 104 | MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 105 | |
| 106 | /*wait till read value is ready */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 107 | timeout = MVGBE_PHY_SMI_TIMEOUT; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 108 | |
| 109 | do { |
| 110 | /* read smi register */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 111 | smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 112 | if (timeout-- == 0) { |
| 113 | printf("Err..(%s) SMI read ready timeout\n", |
| 114 | __FUNCTION__); |
| 115 | return -EFAULT; |
| 116 | } |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 117 | } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK)); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 118 | |
| 119 | /* Wait for the data to update in the SMI register */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 120 | for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++) |
| 121 | ; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 122 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 123 | *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 124 | |
| 125 | debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr, |
| 126 | reg_ofs, *data); |
| 127 | |
| 128 | return 0; |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * smi_reg_write - imiiphy_write callback function. |
| 133 | * |
| 134 | * Returns 0 if write succeed, -EINVAL on bad parameters |
| 135 | * -ETIME on timeout |
| 136 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 137 | static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 138 | { |
| 139 | struct eth_device *dev = eth_get_dev_by_name(devname); |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 140 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 141 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 142 | u32 smi_reg; |
Simon Kagstrom | 4d0941c | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 143 | u32 timeout; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 144 | |
| 145 | /* Phyadr write request*/ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 146 | if (phy_adr == MV_PHY_ADR_REQUEST && |
| 147 | reg_ofs == MV_PHY_ADR_REQUEST) { |
| 148 | MVGBE_REG_WR(regs->phyadr, data); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 149 | return 0; |
| 150 | } |
| 151 | |
| 152 | /* check parameters */ |
| 153 | if (phy_adr > PHYADR_MASK) { |
| 154 | printf("Err..(%s) Invalid phy address\n", __FUNCTION__); |
| 155 | return -EINVAL; |
| 156 | } |
| 157 | if (reg_ofs > PHYREG_MASK) { |
| 158 | printf("Err..(%s) Invalid register offset\n", __FUNCTION__); |
| 159 | return -EINVAL; |
| 160 | } |
| 161 | |
| 162 | /* wait till the SMI is not busy */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 163 | timeout = MVGBE_PHY_SMI_TIMEOUT; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 164 | do { |
| 165 | /* read smi register */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 166 | smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 167 | if (timeout-- == 0) { |
| 168 | printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); |
| 169 | return -ETIME; |
| 170 | } |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 171 | } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 172 | |
| 173 | /* fill the phy addr and reg offset and write opcode and data */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 174 | smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS); |
| 175 | smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) |
| 176 | | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS); |
| 177 | smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 178 | |
| 179 | /* write the smi register */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 180 | MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 181 | |
| 182 | return 0; |
| 183 | } |
| 184 | |
| 185 | /* Stop and checks all queues */ |
| 186 | static void stop_queue(u32 * qreg) |
| 187 | { |
| 188 | u32 reg_data; |
| 189 | |
| 190 | reg_data = readl(qreg); |
| 191 | |
| 192 | if (reg_data & 0xFF) { |
| 193 | /* Issue stop command for active channels only */ |
| 194 | writel((reg_data << 8), qreg); |
| 195 | |
| 196 | /* Wait for all queue activity to terminate. */ |
| 197 | do { |
| 198 | /* |
| 199 | * Check port cause register that all queues |
| 200 | * are stopped |
| 201 | */ |
| 202 | reg_data = readl(qreg); |
| 203 | } |
| 204 | while (reg_data & 0xFF); |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | /* |
| 209 | * set_access_control - Config address decode parameters for Ethernet unit |
| 210 | * |
| 211 | * This function configures the address decode parameters for the Gigabit |
| 212 | * Ethernet Controller according the given parameters struct. |
| 213 | * |
| 214 | * @regs Register struct pointer. |
| 215 | * @param Address decode parameter struct. |
| 216 | */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 217 | static void set_access_control(struct mvgbe_registers *regs, |
| 218 | struct mvgbe_winparam *param) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 219 | { |
| 220 | u32 access_prot_reg; |
| 221 | |
| 222 | /* Set access control register */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 223 | access_prot_reg = MVGBE_REG_RD(regs->epap); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 224 | /* clear window permission */ |
| 225 | access_prot_reg &= (~(3 << (param->win * 2))); |
| 226 | access_prot_reg |= (param->access_ctrl << (param->win * 2)); |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 227 | MVGBE_REG_WR(regs->epap, access_prot_reg); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 228 | |
| 229 | /* Set window Size reg (SR) */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 230 | MVGBE_REG_WR(regs->barsz[param->win].size, |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 231 | (((param->size / 0x10000) - 1) << 16)); |
| 232 | |
| 233 | /* Set window Base address reg (BA) */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 234 | MVGBE_REG_WR(regs->barsz[param->win].bar, |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 235 | (param->target | param->attrib | param->base_addr)); |
| 236 | /* High address remap reg (HARR) */ |
| 237 | if (param->win < 4) |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 238 | MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 239 | |
| 240 | /* Base address enable reg (BARER) */ |
| 241 | if (param->enable == 1) |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 242 | MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win)); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 243 | else |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 244 | MVGBE_REG_BITS_SET(regs->bare, (1 << param->win)); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 245 | } |
| 246 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 247 | static void set_dram_access(struct mvgbe_registers *regs) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 248 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 249 | struct mvgbe_winparam win_param; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 250 | int i; |
| 251 | |
| 252 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 253 | /* Set access parameters for DRAM bank i */ |
| 254 | win_param.win = i; /* Use Ethernet window i */ |
| 255 | /* Window target - DDR */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 256 | win_param.target = MVGBE_TARGET_DRAM; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 257 | /* Enable full access */ |
| 258 | win_param.access_ctrl = EWIN_ACCESS_FULL; |
| 259 | win_param.high_addr = 0; |
Albert Aribaud | a756407 | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 260 | /* Get bank base and size */ |
| 261 | win_param.base_addr = gd->bd->bi_dram[i].start; |
| 262 | win_param.size = gd->bd->bi_dram[i].size; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 263 | if (win_param.size == 0) |
| 264 | win_param.enable = 0; |
| 265 | else |
| 266 | win_param.enable = 1; /* Enable the access */ |
| 267 | |
| 268 | /* Enable DRAM bank */ |
| 269 | switch (i) { |
| 270 | case 0: |
| 271 | win_param.attrib = EBAR_DRAM_CS0; |
| 272 | break; |
| 273 | case 1: |
| 274 | win_param.attrib = EBAR_DRAM_CS1; |
| 275 | break; |
| 276 | case 2: |
| 277 | win_param.attrib = EBAR_DRAM_CS2; |
| 278 | break; |
| 279 | case 3: |
| 280 | win_param.attrib = EBAR_DRAM_CS3; |
| 281 | break; |
| 282 | default: |
Albert Aribaud | a756407 | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 283 | /* invalid bank, disable access */ |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 284 | win_param.enable = 0; |
| 285 | win_param.attrib = 0; |
| 286 | break; |
| 287 | } |
| 288 | /* Set the access control for address window(EPAPR) RD/WR */ |
| 289 | set_access_control(regs, &win_param); |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | /* |
| 294 | * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables |
| 295 | * |
| 296 | * Go through all the DA filter tables (Unicast, Special Multicast & Other |
| 297 | * Multicast) and set each entry to 0. |
| 298 | */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 299 | static void port_init_mac_tables(struct mvgbe_registers *regs) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 300 | { |
| 301 | int table_index; |
| 302 | |
| 303 | /* Clear DA filter unicast table (Ex_dFUT) */ |
| 304 | for (table_index = 0; table_index < 4; ++table_index) |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 305 | MVGBE_REG_WR(regs->dfut[table_index], 0); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 306 | |
| 307 | for (table_index = 0; table_index < 64; ++table_index) { |
| 308 | /* Clear DA filter special multicast table (Ex_dFSMT) */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 309 | MVGBE_REG_WR(regs->dfsmt[table_index], 0); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 310 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 311 | MVGBE_REG_WR(regs->dfomt[table_index], 0); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 312 | } |
| 313 | } |
| 314 | |
| 315 | /* |
| 316 | * port_uc_addr - This function Set the port unicast address table |
| 317 | * |
| 318 | * This function locates the proper entry in the Unicast table for the |
| 319 | * specified MAC nibble and sets its properties according to function |
| 320 | * parameters. |
| 321 | * This function add/removes MAC addresses from the port unicast address |
| 322 | * table. |
| 323 | * |
| 324 | * @uc_nibble Unicast MAC Address last nibble. |
| 325 | * @option 0 = Add, 1 = remove address. |
| 326 | * |
| 327 | * RETURN: 1 if output succeeded. 0 if option parameter is invalid. |
| 328 | */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 329 | static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble, |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 330 | int option) |
| 331 | { |
| 332 | u32 unicast_reg; |
| 333 | u32 tbl_offset; |
| 334 | u32 reg_offset; |
| 335 | |
| 336 | /* Locate the Unicast table entry */ |
| 337 | uc_nibble = (0xf & uc_nibble); |
| 338 | /* Register offset from unicast table base */ |
| 339 | tbl_offset = (uc_nibble / 4); |
| 340 | /* Entry offset within the above register */ |
| 341 | reg_offset = uc_nibble % 4; |
| 342 | |
| 343 | switch (option) { |
| 344 | case REJECT_MAC_ADDR: |
| 345 | /* |
| 346 | * Clear accepts frame bit at specified unicast |
| 347 | * DA table entry |
| 348 | */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 349 | unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 350 | unicast_reg &= (0xFF << (8 * reg_offset)); |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 351 | MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 352 | break; |
| 353 | case ACCEPT_MAC_ADDR: |
| 354 | /* Set accepts frame bit at unicast DA filter table entry */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 355 | unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 356 | unicast_reg &= (0xFF << (8 * reg_offset)); |
| 357 | unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 358 | MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 359 | break; |
| 360 | default: |
| 361 | return 0; |
| 362 | } |
| 363 | return 1; |
| 364 | } |
| 365 | |
| 366 | /* |
| 367 | * port_uc_addr_set - This function Set the port Unicast address. |
| 368 | */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 369 | static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 370 | { |
| 371 | u32 mac_h; |
| 372 | u32 mac_l; |
| 373 | |
| 374 | mac_l = (p_addr[4] << 8) | (p_addr[5]); |
| 375 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | |
| 376 | (p_addr[3] << 0); |
| 377 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 378 | MVGBE_REG_WR(regs->macal, mac_l); |
| 379 | MVGBE_REG_WR(regs->macah, mac_h); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 380 | |
| 381 | /* Accept frames of this address */ |
| 382 | port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); |
| 383 | } |
| 384 | |
| 385 | /* |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 386 | * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 387 | */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 388 | static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 389 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 390 | struct mvgbe_rxdesc *p_rx_desc; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 391 | int i; |
| 392 | |
| 393 | /* initialize the Rx descriptors ring */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 394 | p_rx_desc = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 395 | for (i = 0; i < RINGSZ; i++) { |
| 396 | p_rx_desc->cmd_sts = |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 397 | MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 398 | p_rx_desc->buf_size = PKTSIZE_ALIGN; |
| 399 | p_rx_desc->byte_cnt = 0; |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 400 | p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 401 | if (i == (RINGSZ - 1)) |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 402 | p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 403 | else { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 404 | p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *) |
| 405 | ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 406 | p_rx_desc = p_rx_desc->nxtdesc_p; |
| 407 | } |
| 408 | } |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 409 | dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 410 | } |
| 411 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 412 | static int mvgbe_init(struct eth_device *dev) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 413 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 414 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 415 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 9841dec | 2009-09-09 15:59:19 +0530 | [diff] [blame] | 416 | #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ |
| 417 | && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) |
Simon Kagstrom | 15cc5a6 | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 418 | int i; |
Prafulla Wadaskar | 9841dec | 2009-09-09 15:59:19 +0530 | [diff] [blame] | 419 | #endif |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 420 | /* setup RX rings */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 421 | mvgbe_init_rx_desc_ring(dmvgbe); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 422 | |
| 423 | /* Clear the ethernet port interrupts */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 424 | MVGBE_REG_WR(regs->ic, 0); |
| 425 | MVGBE_REG_WR(regs->ice, 0); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 426 | /* Unmask RX buffer and TX end interrupt */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 427 | MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 428 | /* Unmask phy and link status changes interrupts */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 429 | MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 430 | |
| 431 | set_dram_access(regs); |
| 432 | port_init_mac_tables(regs); |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 433 | port_uc_addr_set(regs, dmvgbe->dev.enetaddr); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 434 | |
| 435 | /* Assign port configuration and command. */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 436 | MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL); |
| 437 | MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); |
| 438 | MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 439 | |
| 440 | /* Assign port SDMA configuration */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 441 | MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); |
| 442 | MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); |
| 443 | MVGBE_REG_WR(regs->tqx[0].tqxtbc, |
| 444 | (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 445 | /* Turn off the port/RXUQ bandwidth limitation */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 446 | MVGBE_REG_WR(regs->pmtu, 0); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 447 | |
| 448 | /* Set maximum receive buffer to 9700 bytes */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 449 | MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE |
| 450 | | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 451 | |
Prafulla Wadaskar | 60ee8a2 | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 452 | /* Enable port initially */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 453 | MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); |
Prafulla Wadaskar | 60ee8a2 | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 454 | |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 455 | /* |
| 456 | * Set ethernet MTU for leaky bucket mechanism to 0 - this will |
| 457 | * disable the leaky bucket mechanism . |
| 458 | */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 459 | MVGBE_REG_WR(regs->pmtu, 0); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 460 | |
| 461 | /* Assignment of Rx CRDB of given RXUQ */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 462 | MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr); |
Albert Aribaud | cc2b8e3 | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 463 | /* ensure previous write is done before enabling Rx DMA */ |
| 464 | isb(); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 465 | /* Enable port Rx. */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 466 | MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 467 | |
| 468 | #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ |
| 469 | && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) |
Simon Kagstrom | 15cc5a6 | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 470 | /* Wait up to 5s for the link status */ |
| 471 | for (i = 0; i < 5; i++) { |
| 472 | u16 phyadr; |
| 473 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 474 | miiphy_read(dev->name, MV_PHY_ADR_REQUEST, |
| 475 | MV_PHY_ADR_REQUEST, &phyadr); |
Simon Kagstrom | 15cc5a6 | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 476 | /* Return if we get link up */ |
| 477 | if (miiphy_link(dev->name, phyadr)) |
| 478 | return 0; |
| 479 | udelay(1000000); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 480 | } |
Simon Kagstrom | 15cc5a6 | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 481 | |
| 482 | printf("No link on %s\n", dev->name); |
| 483 | return -1; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 484 | #endif |
| 485 | return 0; |
| 486 | } |
| 487 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 488 | static int mvgbe_halt(struct eth_device *dev) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 489 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 490 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 491 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 492 | |
| 493 | /* Disable all gigE address decoder */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 494 | MVGBE_REG_WR(regs->bare, 0x3f); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 495 | |
| 496 | stop_queue(®s->tqc); |
| 497 | stop_queue(®s->rqc); |
| 498 | |
Prafulla Wadaskar | 60ee8a2 | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 499 | /* Disable port */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 500 | MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 501 | /* Set port is not reset */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 502 | MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 503 | #ifdef CONFIG_SYS_MII_MODE |
| 504 | /* Set MMI interface up */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 505 | MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 506 | #endif |
| 507 | /* Disable & mask ethernet port interrupts */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 508 | MVGBE_REG_WR(regs->ic, 0); |
| 509 | MVGBE_REG_WR(regs->ice, 0); |
| 510 | MVGBE_REG_WR(regs->pim, 0); |
| 511 | MVGBE_REG_WR(regs->peim, 0); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 512 | |
| 513 | return 0; |
| 514 | } |
| 515 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 516 | static int mvgbe_write_hwaddr(struct eth_device *dev) |
Prafulla Wadaskar | 7dae2eb | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 517 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 518 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 519 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 7dae2eb | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 520 | |
| 521 | /* Programs net device MAC address after initialization */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 522 | port_uc_addr_set(regs, dmvgbe->dev.enetaddr); |
Prafulla Wadaskar | 7dae2eb | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 523 | return 0; |
| 524 | } |
| 525 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 526 | static int mvgbe_send(struct eth_device *dev, void *dataptr, |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 527 | int datasize) |
| 528 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 529 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 530 | struct mvgbe_registers *regs = dmvgbe->regs; |
| 531 | struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc; |
Simon Kagstrom | e9220b3 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 532 | void *p = (void *)dataptr; |
Simon Kagstrom | 4d0941c | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 533 | u32 cmd_sts; |
Anatolij Gustschin | da42f24 | 2011-11-19 08:59:36 +0000 | [diff] [blame] | 534 | u32 txuq0_reg_addr; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 535 | |
Simon Kagstrom | e9220b3 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 536 | /* Copy buffer if it's misaligned */ |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 537 | if ((u32) dataptr & 0x07) { |
Simon Kagstrom | e9220b3 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 538 | if (datasize > PKTSIZE_ALIGN) { |
| 539 | printf("Non-aligned data too large (%d)\n", |
| 540 | datasize); |
| 541 | return -1; |
| 542 | } |
| 543 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 544 | memcpy(dmvgbe->p_aligned_txbuf, p, datasize); |
| 545 | p = dmvgbe->p_aligned_txbuf; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 546 | } |
Simon Kagstrom | e9220b3 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 547 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 548 | p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; |
| 549 | p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; |
| 550 | p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; |
| 551 | p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; |
Simon Kagstrom | e9220b3 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 552 | p_txdesc->buf_ptr = (u8 *) p; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 553 | p_txdesc->byte_cnt = datasize; |
| 554 | |
Albert Aribaud | cc2b8e3 | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 555 | /* Set this tc desc as zeroth TXUQ */ |
Anatolij Gustschin | da42f24 | 2011-11-19 08:59:36 +0000 | [diff] [blame] | 556 | txuq0_reg_addr = (u32)®s->tcqdp[TXUQ]; |
| 557 | writel((u32) p_txdesc, txuq0_reg_addr); |
Albert Aribaud | cc2b8e3 | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 558 | |
| 559 | /* ensure tx desc writes above are performed before we start Tx DMA */ |
| 560 | isb(); |
| 561 | |
| 562 | /* Apply send command using zeroth TXUQ */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 563 | MVGBE_REG_WR(regs->tqc, (1 << TXUQ)); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 564 | |
| 565 | /* |
| 566 | * wait for packet xmit completion |
| 567 | */ |
Simon Kagstrom | 4d0941c | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 568 | cmd_sts = readl(&p_txdesc->cmd_sts); |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 569 | while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 570 | /* return fail if error is detected */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 571 | if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == |
| 572 | (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) && |
| 573 | cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 574 | printf("Err..(%s) in xmit packet\n", __FUNCTION__); |
| 575 | return -1; |
| 576 | } |
Simon Kagstrom | 4d0941c | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 577 | cmd_sts = readl(&p_txdesc->cmd_sts); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 578 | }; |
| 579 | return 0; |
| 580 | } |
| 581 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 582 | static int mvgbe_recv(struct eth_device *dev) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 583 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 584 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 585 | struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; |
Simon Kagstrom | 4d0941c | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 586 | u32 cmd_sts; |
| 587 | u32 timeout = 0; |
Anatolij Gustschin | da42f24 | 2011-11-19 08:59:36 +0000 | [diff] [blame] | 588 | u32 rxdesc_curr_addr; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 589 | |
| 590 | /* wait untill rx packet available or timeout */ |
| 591 | do { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 592 | if (timeout < MVGBE_PHY_SMI_TIMEOUT) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 593 | timeout++; |
| 594 | else { |
| 595 | debug("%s time out...\n", __FUNCTION__); |
| 596 | return -1; |
| 597 | } |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 598 | } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 599 | |
| 600 | if (p_rxdesc_curr->byte_cnt != 0) { |
| 601 | debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", |
| 602 | __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt, |
| 603 | (u32) p_rxdesc_curr->buf_ptr, |
| 604 | (u32) p_rxdesc_curr->cmd_sts); |
| 605 | } |
| 606 | |
| 607 | /* |
| 608 | * In case received a packet without first/last bits on |
| 609 | * OR the error summary bit is on, |
| 610 | * the packets needs to be dropeed. |
| 611 | */ |
Simon Kagstrom | 4d0941c | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 612 | cmd_sts = readl(&p_rxdesc_curr->cmd_sts); |
| 613 | |
| 614 | if ((cmd_sts & |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 615 | (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) |
| 616 | != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) { |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 617 | |
| 618 | printf("Err..(%s) Dropping packet spread on" |
| 619 | " multiple descriptors\n", __FUNCTION__); |
| 620 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 621 | } else if (cmd_sts & MVGBE_ERROR_SUMMARY) { |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 622 | |
| 623 | printf("Err..(%s) Dropping packet with errors\n", |
| 624 | __FUNCTION__); |
| 625 | |
| 626 | } else { |
| 627 | /* !!! call higher layer processing */ |
| 628 | debug("%s: Sending Received packet to" |
| 629 | " upper layer (NetReceive)\n", __FUNCTION__); |
| 630 | |
| 631 | /* let the upper layer handle the packet */ |
| 632 | NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET), |
| 633 | (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); |
| 634 | } |
| 635 | /* |
| 636 | * free these descriptors and point next in the ring |
| 637 | */ |
| 638 | p_rxdesc_curr->cmd_sts = |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 639 | MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 640 | p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; |
| 641 | p_rxdesc_curr->byte_cnt = 0; |
| 642 | |
Anatolij Gustschin | da42f24 | 2011-11-19 08:59:36 +0000 | [diff] [blame] | 643 | rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr; |
| 644 | writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr); |
Simon Kagstrom | 4d0941c | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 645 | |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 646 | return 0; |
| 647 | } |
| 648 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 649 | int mvgbe_initialize(bd_t *bis) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 650 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 651 | struct mvgbe_device *dmvgbe; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 652 | struct eth_device *dev; |
| 653 | int devnum; |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 654 | u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 655 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 656 | for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 657 | /*skip if port is configured not to use */ |
| 658 | if (used_ports[devnum] == 0) |
| 659 | continue; |
| 660 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 661 | dmvgbe = malloc(sizeof(struct mvgbe_device)); |
| 662 | |
| 663 | if (!dmvgbe) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 664 | goto error1; |
| 665 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 666 | memset(dmvgbe, 0, sizeof(struct mvgbe_device)); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 667 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 668 | dmvgbe->p_rxdesc = |
| 669 | (struct mvgbe_rxdesc *)memalign(PKTALIGN, |
| 670 | MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1); |
| 671 | |
| 672 | if (!dmvgbe->p_rxdesc) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 673 | goto error2; |
| 674 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 675 | dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, |
| 676 | RINGSZ*PKTSIZE_ALIGN + 1); |
| 677 | |
| 678 | if (!dmvgbe->p_rxbuf) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 679 | goto error3; |
| 680 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 681 | dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); |
| 682 | |
| 683 | if (!dmvgbe->p_aligned_txbuf) |
Simon Kagstrom | e9220b3 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 684 | goto error4; |
| 685 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 686 | dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign( |
| 687 | PKTALIGN, sizeof(struct mvgbe_txdesc) + 1); |
| 688 | |
| 689 | if (!dmvgbe->p_txdesc) { |
| 690 | free(dmvgbe->p_aligned_txbuf); |
| 691 | error4: |
| 692 | free(dmvgbe->p_rxbuf); |
| 693 | error3: |
| 694 | free(dmvgbe->p_rxdesc); |
| 695 | error2: |
| 696 | free(dmvgbe); |
| 697 | error1: |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 698 | printf("Err.. %s Failed to allocate memory\n", |
| 699 | __FUNCTION__); |
| 700 | return -1; |
| 701 | } |
| 702 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 703 | dev = &dmvgbe->dev; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 704 | |
Mike Frysinger | 6b300dc | 2011-11-10 14:11:04 +0000 | [diff] [blame] | 705 | /* must be less than sizeof(dev->name) */ |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 706 | sprintf(dev->name, "egiga%d", devnum); |
| 707 | |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 708 | switch (devnum) { |
| 709 | case 0: |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 710 | dmvgbe->regs = (void *)MVGBE0_BASE; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 711 | break; |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 712 | #if defined(MVGBE1_BASE) |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 713 | case 1: |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 714 | dmvgbe->regs = (void *)MVGBE1_BASE; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 715 | break; |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 716 | #endif |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 717 | default: /* this should never happen */ |
| 718 | printf("Err..(%s) Invalid device number %d\n", |
| 719 | __FUNCTION__, devnum); |
| 720 | return -1; |
| 721 | } |
| 722 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 723 | dev->init = (void *)mvgbe_init; |
| 724 | dev->halt = (void *)mvgbe_halt; |
| 725 | dev->send = (void *)mvgbe_send; |
| 726 | dev->recv = (void *)mvgbe_recv; |
| 727 | dev->write_hwaddr = (void *)mvgbe_write_hwaddr; |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 728 | |
| 729 | eth_register(dev); |
| 730 | |
| 731 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
| 732 | miiphy_register(dev->name, smi_reg_read, smi_reg_write); |
| 733 | /* Set phy address of the port */ |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 734 | miiphy_write(dev->name, MV_PHY_ADR_REQUEST, |
| 735 | MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); |
Prafulla Wadaskar | b7a280d | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 736 | #endif |
| 737 | } |
| 738 | return 0; |
Prafulla Wadaskar | 12618ef | 2009-07-01 20:34:51 +0200 | [diff] [blame] | 739 | } |