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Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2003
7 * Ingo Assmus <ingo.assmus@keymile.com>
8 *
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 * MA 02110-1301 USA
29 */
30
31#include <common.h>
32#include <net.h>
33#include <malloc.h>
34#include <miiphy.h>
Lei Wen298ae912011-10-18 20:11:42 +053035#include <asm/io.h>
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053036#include <asm/errno.h>
37#include <asm/types.h>
Lei Wen298ae912011-10-18 20:11:42 +053038#include <asm/system.h>
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053039#include <asm/byteorder.h>
Anatolij Gustschinc8b222e2011-10-29 10:09:22 +000040#include <asm/arch/cpu.h>
Albert Aribaude91d7d32010-07-12 22:24:28 +020041
42#if defined(CONFIG_KIRKWOOD)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053043#include <asm/arch/kirkwood.h>
Albert Aribaud8a995232010-07-12 22:24:29 +020044#elif defined(CONFIG_ORION5X)
45#include <asm/arch/orion5x.h>
Albert Aribaude91d7d32010-07-12 22:24:28 +020046#endif
47
Albert Aribaud0d027d92010-07-12 22:24:27 +020048#include "mvgbe.h"
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053049
Albert Aribauda7564072010-07-05 20:15:25 +020050DECLARE_GLOBAL_DATA_PTR;
51
Albert Aribaude91d7d32010-07-12 22:24:28 +020052#define MV_PHY_ADR_REQUEST 0xee
53#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
Simon Kagstromab9ca512009-08-20 10:12:28 +020054
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053055/*
56 * smi_reg_read - miiphy_read callback function.
57 *
58 * Returns 16bit phy register value, or 0xffff on error
59 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040060static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053061{
62 struct eth_device *dev = eth_get_dev_by_name(devname);
Albert Aribaude91d7d32010-07-12 22:24:28 +020063 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
64 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053065 u32 smi_reg;
Simon Kagstrom4d0941c2009-07-08 13:03:18 +020066 u32 timeout;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053067
68 /* Phyadr read request */
Albert Aribaude91d7d32010-07-12 22:24:28 +020069 if (phy_adr == MV_PHY_ADR_REQUEST &&
70 reg_ofs == MV_PHY_ADR_REQUEST) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053071 /* */
Albert Aribaude91d7d32010-07-12 22:24:28 +020072 *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053073 return 0;
74 }
75 /* check parameters */
76 if (phy_adr > PHYADR_MASK) {
77 printf("Err..(%s) Invalid PHY address %d\n",
78 __FUNCTION__, phy_adr);
79 return -EFAULT;
80 }
81 if (reg_ofs > PHYREG_MASK) {
82 printf("Err..(%s) Invalid register offset %d\n",
83 __FUNCTION__, reg_ofs);
84 return -EFAULT;
85 }
86
Albert Aribaude91d7d32010-07-12 22:24:28 +020087 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053088 /* wait till the SMI is not busy */
89 do {
90 /* read smi register */
Albert Aribaude91d7d32010-07-12 22:24:28 +020091 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053092 if (timeout-- == 0) {
93 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
94 return -EFAULT;
95 }
Albert Aribaude91d7d32010-07-12 22:24:28 +020096 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053097
98 /* fill the phy address and regiser offset and read opcode */
Albert Aribaude91d7d32010-07-12 22:24:28 +020099 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
100 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
101 | MVGBE_PHY_SMI_OPCODE_READ;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530102
103 /* write the smi register */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200104 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530105
106 /*wait till read value is ready */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200107 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530108
109 do {
110 /* read smi register */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200111 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530112 if (timeout-- == 0) {
113 printf("Err..(%s) SMI read ready timeout\n",
114 __FUNCTION__);
115 return -EFAULT;
116 }
Albert Aribaude91d7d32010-07-12 22:24:28 +0200117 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530118
119 /* Wait for the data to update in the SMI register */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200120 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
121 ;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530122
Albert Aribaude91d7d32010-07-12 22:24:28 +0200123 *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530124
125 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
126 reg_ofs, *data);
127
128 return 0;
129}
130
131/*
132 * smi_reg_write - imiiphy_write callback function.
133 *
134 * Returns 0 if write succeed, -EINVAL on bad parameters
135 * -ETIME on timeout
136 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400137static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530138{
139 struct eth_device *dev = eth_get_dev_by_name(devname);
Albert Aribaude91d7d32010-07-12 22:24:28 +0200140 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
141 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530142 u32 smi_reg;
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200143 u32 timeout;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530144
145 /* Phyadr write request*/
Albert Aribaude91d7d32010-07-12 22:24:28 +0200146 if (phy_adr == MV_PHY_ADR_REQUEST &&
147 reg_ofs == MV_PHY_ADR_REQUEST) {
148 MVGBE_REG_WR(regs->phyadr, data);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530149 return 0;
150 }
151
152 /* check parameters */
153 if (phy_adr > PHYADR_MASK) {
154 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
155 return -EINVAL;
156 }
157 if (reg_ofs > PHYREG_MASK) {
158 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
159 return -EINVAL;
160 }
161
162 /* wait till the SMI is not busy */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200163 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530164 do {
165 /* read smi register */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200166 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530167 if (timeout-- == 0) {
168 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
169 return -ETIME;
170 }
Albert Aribaude91d7d32010-07-12 22:24:28 +0200171 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530172
173 /* fill the phy addr and reg offset and write opcode and data */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200174 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
175 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
176 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
177 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530178
179 /* write the smi register */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200180 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530181
182 return 0;
183}
184
185/* Stop and checks all queues */
186static void stop_queue(u32 * qreg)
187{
188 u32 reg_data;
189
190 reg_data = readl(qreg);
191
192 if (reg_data & 0xFF) {
193 /* Issue stop command for active channels only */
194 writel((reg_data << 8), qreg);
195
196 /* Wait for all queue activity to terminate. */
197 do {
198 /*
199 * Check port cause register that all queues
200 * are stopped
201 */
202 reg_data = readl(qreg);
203 }
204 while (reg_data & 0xFF);
205 }
206}
207
208/*
209 * set_access_control - Config address decode parameters for Ethernet unit
210 *
211 * This function configures the address decode parameters for the Gigabit
212 * Ethernet Controller according the given parameters struct.
213 *
214 * @regs Register struct pointer.
215 * @param Address decode parameter struct.
216 */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200217static void set_access_control(struct mvgbe_registers *regs,
218 struct mvgbe_winparam *param)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530219{
220 u32 access_prot_reg;
221
222 /* Set access control register */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200223 access_prot_reg = MVGBE_REG_RD(regs->epap);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530224 /* clear window permission */
225 access_prot_reg &= (~(3 << (param->win * 2)));
226 access_prot_reg |= (param->access_ctrl << (param->win * 2));
Albert Aribaude91d7d32010-07-12 22:24:28 +0200227 MVGBE_REG_WR(regs->epap, access_prot_reg);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530228
229 /* Set window Size reg (SR) */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200230 MVGBE_REG_WR(regs->barsz[param->win].size,
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530231 (((param->size / 0x10000) - 1) << 16));
232
233 /* Set window Base address reg (BA) */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200234 MVGBE_REG_WR(regs->barsz[param->win].bar,
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530235 (param->target | param->attrib | param->base_addr));
236 /* High address remap reg (HARR) */
237 if (param->win < 4)
Albert Aribaude91d7d32010-07-12 22:24:28 +0200238 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530239
240 /* Base address enable reg (BARER) */
241 if (param->enable == 1)
Albert Aribaude91d7d32010-07-12 22:24:28 +0200242 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530243 else
Albert Aribaude91d7d32010-07-12 22:24:28 +0200244 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530245}
246
Albert Aribaude91d7d32010-07-12 22:24:28 +0200247static void set_dram_access(struct mvgbe_registers *regs)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530248{
Albert Aribaude91d7d32010-07-12 22:24:28 +0200249 struct mvgbe_winparam win_param;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530250 int i;
251
252 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
253 /* Set access parameters for DRAM bank i */
254 win_param.win = i; /* Use Ethernet window i */
255 /* Window target - DDR */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200256 win_param.target = MVGBE_TARGET_DRAM;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530257 /* Enable full access */
258 win_param.access_ctrl = EWIN_ACCESS_FULL;
259 win_param.high_addr = 0;
Albert Aribauda7564072010-07-05 20:15:25 +0200260 /* Get bank base and size */
261 win_param.base_addr = gd->bd->bi_dram[i].start;
262 win_param.size = gd->bd->bi_dram[i].size;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530263 if (win_param.size == 0)
264 win_param.enable = 0;
265 else
266 win_param.enable = 1; /* Enable the access */
267
268 /* Enable DRAM bank */
269 switch (i) {
270 case 0:
271 win_param.attrib = EBAR_DRAM_CS0;
272 break;
273 case 1:
274 win_param.attrib = EBAR_DRAM_CS1;
275 break;
276 case 2:
277 win_param.attrib = EBAR_DRAM_CS2;
278 break;
279 case 3:
280 win_param.attrib = EBAR_DRAM_CS3;
281 break;
282 default:
Albert Aribauda7564072010-07-05 20:15:25 +0200283 /* invalid bank, disable access */
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530284 win_param.enable = 0;
285 win_param.attrib = 0;
286 break;
287 }
288 /* Set the access control for address window(EPAPR) RD/WR */
289 set_access_control(regs, &win_param);
290 }
291}
292
293/*
294 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
295 *
296 * Go through all the DA filter tables (Unicast, Special Multicast & Other
297 * Multicast) and set each entry to 0.
298 */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200299static void port_init_mac_tables(struct mvgbe_registers *regs)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530300{
301 int table_index;
302
303 /* Clear DA filter unicast table (Ex_dFUT) */
304 for (table_index = 0; table_index < 4; ++table_index)
Albert Aribaude91d7d32010-07-12 22:24:28 +0200305 MVGBE_REG_WR(regs->dfut[table_index], 0);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530306
307 for (table_index = 0; table_index < 64; ++table_index) {
308 /* Clear DA filter special multicast table (Ex_dFSMT) */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200309 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530310 /* Clear DA filter other multicast table (Ex_dFOMT) */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200311 MVGBE_REG_WR(regs->dfomt[table_index], 0);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530312 }
313}
314
315/*
316 * port_uc_addr - This function Set the port unicast address table
317 *
318 * This function locates the proper entry in the Unicast table for the
319 * specified MAC nibble and sets its properties according to function
320 * parameters.
321 * This function add/removes MAC addresses from the port unicast address
322 * table.
323 *
324 * @uc_nibble Unicast MAC Address last nibble.
325 * @option 0 = Add, 1 = remove address.
326 *
327 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
328 */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200329static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530330 int option)
331{
332 u32 unicast_reg;
333 u32 tbl_offset;
334 u32 reg_offset;
335
336 /* Locate the Unicast table entry */
337 uc_nibble = (0xf & uc_nibble);
338 /* Register offset from unicast table base */
339 tbl_offset = (uc_nibble / 4);
340 /* Entry offset within the above register */
341 reg_offset = uc_nibble % 4;
342
343 switch (option) {
344 case REJECT_MAC_ADDR:
345 /*
346 * Clear accepts frame bit at specified unicast
347 * DA table entry
348 */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200349 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530350 unicast_reg &= (0xFF << (8 * reg_offset));
Albert Aribaude91d7d32010-07-12 22:24:28 +0200351 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530352 break;
353 case ACCEPT_MAC_ADDR:
354 /* Set accepts frame bit at unicast DA filter table entry */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200355 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530356 unicast_reg &= (0xFF << (8 * reg_offset));
357 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
Albert Aribaude91d7d32010-07-12 22:24:28 +0200358 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530359 break;
360 default:
361 return 0;
362 }
363 return 1;
364}
365
366/*
367 * port_uc_addr_set - This function Set the port Unicast address.
368 */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200369static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530370{
371 u32 mac_h;
372 u32 mac_l;
373
374 mac_l = (p_addr[4] << 8) | (p_addr[5]);
375 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
376 (p_addr[3] << 0);
377
Albert Aribaude91d7d32010-07-12 22:24:28 +0200378 MVGBE_REG_WR(regs->macal, mac_l);
379 MVGBE_REG_WR(regs->macah, mac_h);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530380
381 /* Accept frames of this address */
382 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
383}
384
385/*
Albert Aribaude91d7d32010-07-12 22:24:28 +0200386 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530387 */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200388static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530389{
Albert Aribaude91d7d32010-07-12 22:24:28 +0200390 struct mvgbe_rxdesc *p_rx_desc;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530391 int i;
392
393 /* initialize the Rx descriptors ring */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200394 p_rx_desc = dmvgbe->p_rxdesc;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530395 for (i = 0; i < RINGSZ; i++) {
396 p_rx_desc->cmd_sts =
Albert Aribaude91d7d32010-07-12 22:24:28 +0200397 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530398 p_rx_desc->buf_size = PKTSIZE_ALIGN;
399 p_rx_desc->byte_cnt = 0;
Albert Aribaude91d7d32010-07-12 22:24:28 +0200400 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530401 if (i == (RINGSZ - 1))
Albert Aribaude91d7d32010-07-12 22:24:28 +0200402 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530403 else {
Albert Aribaude91d7d32010-07-12 22:24:28 +0200404 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
405 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530406 p_rx_desc = p_rx_desc->nxtdesc_p;
407 }
408 }
Albert Aribaude91d7d32010-07-12 22:24:28 +0200409 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530410}
411
Albert Aribaude91d7d32010-07-12 22:24:28 +0200412static int mvgbe_init(struct eth_device *dev)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530413{
Albert Aribaude91d7d32010-07-12 22:24:28 +0200414 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
415 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar9841dec2009-09-09 15:59:19 +0530416#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
417 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstrom15cc5a62009-08-20 10:13:06 +0200418 int i;
Prafulla Wadaskar9841dec2009-09-09 15:59:19 +0530419#endif
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530420 /* setup RX rings */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200421 mvgbe_init_rx_desc_ring(dmvgbe);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530422
423 /* Clear the ethernet port interrupts */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200424 MVGBE_REG_WR(regs->ic, 0);
425 MVGBE_REG_WR(regs->ice, 0);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530426 /* Unmask RX buffer and TX end interrupt */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200427 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530428 /* Unmask phy and link status changes interrupts */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200429 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530430
431 set_dram_access(regs);
432 port_init_mac_tables(regs);
Albert Aribaude91d7d32010-07-12 22:24:28 +0200433 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530434
435 /* Assign port configuration and command. */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200436 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
437 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
438 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530439
440 /* Assign port SDMA configuration */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200441 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
442 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
443 MVGBE_REG_WR(regs->tqx[0].tqxtbc,
444 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530445 /* Turn off the port/RXUQ bandwidth limitation */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200446 MVGBE_REG_WR(regs->pmtu, 0);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530447
448 /* Set maximum receive buffer to 9700 bytes */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200449 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
450 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530451
Prafulla Wadaskar60ee8a22010-04-06 21:33:08 +0530452 /* Enable port initially */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200453 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
Prafulla Wadaskar60ee8a22010-04-06 21:33:08 +0530454
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530455 /*
456 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
457 * disable the leaky bucket mechanism .
458 */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200459 MVGBE_REG_WR(regs->pmtu, 0);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530460
461 /* Assignment of Rx CRDB of given RXUQ */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200462 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
Albert Aribaudcc2b8e32010-07-10 15:41:29 +0200463 /* ensure previous write is done before enabling Rx DMA */
464 isb();
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530465 /* Enable port Rx. */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200466 MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530467
468#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
469 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstrom15cc5a62009-08-20 10:13:06 +0200470 /* Wait up to 5s for the link status */
471 for (i = 0; i < 5; i++) {
472 u16 phyadr;
473
Albert Aribaude91d7d32010-07-12 22:24:28 +0200474 miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
475 MV_PHY_ADR_REQUEST, &phyadr);
Simon Kagstrom15cc5a62009-08-20 10:13:06 +0200476 /* Return if we get link up */
477 if (miiphy_link(dev->name, phyadr))
478 return 0;
479 udelay(1000000);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530480 }
Simon Kagstrom15cc5a62009-08-20 10:13:06 +0200481
482 printf("No link on %s\n", dev->name);
483 return -1;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530484#endif
485 return 0;
486}
487
Albert Aribaude91d7d32010-07-12 22:24:28 +0200488static int mvgbe_halt(struct eth_device *dev)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530489{
Albert Aribaude91d7d32010-07-12 22:24:28 +0200490 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
491 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530492
493 /* Disable all gigE address decoder */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200494 MVGBE_REG_WR(regs->bare, 0x3f);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530495
496 stop_queue(&regs->tqc);
497 stop_queue(&regs->rqc);
498
Prafulla Wadaskar60ee8a22010-04-06 21:33:08 +0530499 /* Disable port */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200500 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530501 /* Set port is not reset */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200502 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530503#ifdef CONFIG_SYS_MII_MODE
504 /* Set MMI interface up */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200505 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530506#endif
507 /* Disable & mask ethernet port interrupts */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200508 MVGBE_REG_WR(regs->ic, 0);
509 MVGBE_REG_WR(regs->ice, 0);
510 MVGBE_REG_WR(regs->pim, 0);
511 MVGBE_REG_WR(regs->peim, 0);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530512
513 return 0;
514}
515
Albert Aribaude91d7d32010-07-12 22:24:28 +0200516static int mvgbe_write_hwaddr(struct eth_device *dev)
Prafulla Wadaskar7dae2eb2010-04-06 22:21:33 +0530517{
Albert Aribaude91d7d32010-07-12 22:24:28 +0200518 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
519 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar7dae2eb2010-04-06 22:21:33 +0530520
521 /* Programs net device MAC address after initialization */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200522 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
Prafulla Wadaskar7dae2eb2010-04-06 22:21:33 +0530523 return 0;
524}
525
Albert Aribaude91d7d32010-07-12 22:24:28 +0200526static int mvgbe_send(struct eth_device *dev, void *dataptr,
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530527 int datasize)
528{
Albert Aribaude91d7d32010-07-12 22:24:28 +0200529 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
530 struct mvgbe_registers *regs = dmvgbe->regs;
531 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
Simon Kagstrome9220b32009-08-20 10:14:11 +0200532 void *p = (void *)dataptr;
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200533 u32 cmd_sts;
Anatolij Gustschinda42f242011-11-19 08:59:36 +0000534 u32 txuq0_reg_addr;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530535
Simon Kagstrome9220b32009-08-20 10:14:11 +0200536 /* Copy buffer if it's misaligned */
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530537 if ((u32) dataptr & 0x07) {
Simon Kagstrome9220b32009-08-20 10:14:11 +0200538 if (datasize > PKTSIZE_ALIGN) {
539 printf("Non-aligned data too large (%d)\n",
540 datasize);
541 return -1;
542 }
543
Albert Aribaude91d7d32010-07-12 22:24:28 +0200544 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
545 p = dmvgbe->p_aligned_txbuf;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530546 }
Simon Kagstrome9220b32009-08-20 10:14:11 +0200547
Albert Aribaude91d7d32010-07-12 22:24:28 +0200548 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
549 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
550 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
551 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
Simon Kagstrome9220b32009-08-20 10:14:11 +0200552 p_txdesc->buf_ptr = (u8 *) p;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530553 p_txdesc->byte_cnt = datasize;
554
Albert Aribaudcc2b8e32010-07-10 15:41:29 +0200555 /* Set this tc desc as zeroth TXUQ */
Anatolij Gustschinda42f242011-11-19 08:59:36 +0000556 txuq0_reg_addr = (u32)&regs->tcqdp[TXUQ];
557 writel((u32) p_txdesc, txuq0_reg_addr);
Albert Aribaudcc2b8e32010-07-10 15:41:29 +0200558
559 /* ensure tx desc writes above are performed before we start Tx DMA */
560 isb();
561
562 /* Apply send command using zeroth TXUQ */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200563 MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530564
565 /*
566 * wait for packet xmit completion
567 */
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200568 cmd_sts = readl(&p_txdesc->cmd_sts);
Albert Aribaude91d7d32010-07-12 22:24:28 +0200569 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530570 /* return fail if error is detected */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200571 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
572 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
573 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530574 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
575 return -1;
576 }
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200577 cmd_sts = readl(&p_txdesc->cmd_sts);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530578 };
579 return 0;
580}
581
Albert Aribaude91d7d32010-07-12 22:24:28 +0200582static int mvgbe_recv(struct eth_device *dev)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530583{
Albert Aribaude91d7d32010-07-12 22:24:28 +0200584 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
585 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200586 u32 cmd_sts;
587 u32 timeout = 0;
Anatolij Gustschinda42f242011-11-19 08:59:36 +0000588 u32 rxdesc_curr_addr;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530589
590 /* wait untill rx packet available or timeout */
591 do {
Albert Aribaude91d7d32010-07-12 22:24:28 +0200592 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530593 timeout++;
594 else {
595 debug("%s time out...\n", __FUNCTION__);
596 return -1;
597 }
Albert Aribaude91d7d32010-07-12 22:24:28 +0200598 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530599
600 if (p_rxdesc_curr->byte_cnt != 0) {
601 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
602 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
603 (u32) p_rxdesc_curr->buf_ptr,
604 (u32) p_rxdesc_curr->cmd_sts);
605 }
606
607 /*
608 * In case received a packet without first/last bits on
609 * OR the error summary bit is on,
610 * the packets needs to be dropeed.
611 */
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200612 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
613
614 if ((cmd_sts &
Albert Aribaude91d7d32010-07-12 22:24:28 +0200615 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
616 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530617
618 printf("Err..(%s) Dropping packet spread on"
619 " multiple descriptors\n", __FUNCTION__);
620
Albert Aribaude91d7d32010-07-12 22:24:28 +0200621 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530622
623 printf("Err..(%s) Dropping packet with errors\n",
624 __FUNCTION__);
625
626 } else {
627 /* !!! call higher layer processing */
628 debug("%s: Sending Received packet to"
629 " upper layer (NetReceive)\n", __FUNCTION__);
630
631 /* let the upper layer handle the packet */
632 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
633 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
634 }
635 /*
636 * free these descriptors and point next in the ring
637 */
638 p_rxdesc_curr->cmd_sts =
Albert Aribaude91d7d32010-07-12 22:24:28 +0200639 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530640 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
641 p_rxdesc_curr->byte_cnt = 0;
642
Anatolij Gustschinda42f242011-11-19 08:59:36 +0000643 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
644 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200645
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530646 return 0;
647}
648
Albert Aribaude91d7d32010-07-12 22:24:28 +0200649int mvgbe_initialize(bd_t *bis)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530650{
Albert Aribaude91d7d32010-07-12 22:24:28 +0200651 struct mvgbe_device *dmvgbe;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530652 struct eth_device *dev;
653 int devnum;
Albert Aribaude91d7d32010-07-12 22:24:28 +0200654 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530655
Albert Aribaude91d7d32010-07-12 22:24:28 +0200656 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530657 /*skip if port is configured not to use */
658 if (used_ports[devnum] == 0)
659 continue;
660
Albert Aribaude91d7d32010-07-12 22:24:28 +0200661 dmvgbe = malloc(sizeof(struct mvgbe_device));
662
663 if (!dmvgbe)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530664 goto error1;
665
Albert Aribaude91d7d32010-07-12 22:24:28 +0200666 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530667
Albert Aribaude91d7d32010-07-12 22:24:28 +0200668 dmvgbe->p_rxdesc =
669 (struct mvgbe_rxdesc *)memalign(PKTALIGN,
670 MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
671
672 if (!dmvgbe->p_rxdesc)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530673 goto error2;
674
Albert Aribaude91d7d32010-07-12 22:24:28 +0200675 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
676 RINGSZ*PKTSIZE_ALIGN + 1);
677
678 if (!dmvgbe->p_rxbuf)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530679 goto error3;
680
Albert Aribaude91d7d32010-07-12 22:24:28 +0200681 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
682
683 if (!dmvgbe->p_aligned_txbuf)
Simon Kagstrome9220b32009-08-20 10:14:11 +0200684 goto error4;
685
Albert Aribaude91d7d32010-07-12 22:24:28 +0200686 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
687 PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
688
689 if (!dmvgbe->p_txdesc) {
690 free(dmvgbe->p_aligned_txbuf);
691error4:
692 free(dmvgbe->p_rxbuf);
693error3:
694 free(dmvgbe->p_rxdesc);
695error2:
696 free(dmvgbe);
697error1:
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530698 printf("Err.. %s Failed to allocate memory\n",
699 __FUNCTION__);
700 return -1;
701 }
702
Albert Aribaude91d7d32010-07-12 22:24:28 +0200703 dev = &dmvgbe->dev;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530704
Mike Frysinger6b300dc2011-11-10 14:11:04 +0000705 /* must be less than sizeof(dev->name) */
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530706 sprintf(dev->name, "egiga%d", devnum);
707
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530708 switch (devnum) {
709 case 0:
Albert Aribaude91d7d32010-07-12 22:24:28 +0200710 dmvgbe->regs = (void *)MVGBE0_BASE;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530711 break;
Albert Aribaude91d7d32010-07-12 22:24:28 +0200712#if defined(MVGBE1_BASE)
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530713 case 1:
Albert Aribaude91d7d32010-07-12 22:24:28 +0200714 dmvgbe->regs = (void *)MVGBE1_BASE;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530715 break;
Albert Aribaude91d7d32010-07-12 22:24:28 +0200716#endif
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530717 default: /* this should never happen */
718 printf("Err..(%s) Invalid device number %d\n",
719 __FUNCTION__, devnum);
720 return -1;
721 }
722
Albert Aribaude91d7d32010-07-12 22:24:28 +0200723 dev->init = (void *)mvgbe_init;
724 dev->halt = (void *)mvgbe_halt;
725 dev->send = (void *)mvgbe_send;
726 dev->recv = (void *)mvgbe_recv;
727 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530728
729 eth_register(dev);
730
731#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
732 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
733 /* Set phy address of the port */
Albert Aribaude91d7d32010-07-12 22:24:28 +0200734 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
735 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530736#endif
737 }
738 return 0;
Prafulla Wadaskar12618ef2009-07-01 20:34:51 +0200739}