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Daniel Hellstrom73caf572008-03-28 10:20:43 +01001/* Configuration header file for LEON2 GRSIM.
2 *
3 * (C) Copyright 2003-2005
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2007
7 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H__
29#define __CONFIG_H__
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 *
35 * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1.
36 *
37 * TSIM command
38 * tsim-leon -sdram 0 -ram 32000 -rom 8192 -mmu
39 *
40 */
41
42#define CONFIG_LEON2 /* This is an LEON2 CPU */
43#define CONFIG_LEON 1 /* This is an LEON CPU */
44#define CONFIG_GRSIM 0 /* ... not running on GRSIM */
45#define CONFIG_TSIM 1 /* ... running on TSIM */
46
47/* CPU / AMBA BUS configuration */
Wolfgang Denka1be4762008-05-20 16:00:29 +020048#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
Daniel Hellstrom73caf572008-03-28 10:20:43 +010049
50/* Number of SPARC register windows */
51#define CFG_SPARC_NWINDOWS 8
52
53/*
54 * Serial console configuration
55 */
56#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
57#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
58
59/* Partitions */
60#define CONFIG_DOS_PARTITION
61#define CONFIG_MAC_PARTITION
62#define CONFIG_ISO_PARTITION
63
64/*
65 * Supported commands
66 */
67#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
68#define CONFIG_CMD_BDI /* bdinfo */
69#define CONFIG_CMD_CONSOLE /* coninfo */
70#define CONFIG_CMD_DIAG
71#define CONFIG_CMD_ECHO /* echo arguments */
72#define CONFIG_CMD_FPGA /* FPGA configuration Support */
73#define CONFIG_CMD_IRQ
74#define CONFIG_CMD_ITEST /* Integer (and string) test */
75#define CONFIG_CMD_LOADB /* loadb */
76#define CONFIG_CMD_LOADS /* loads */
77#define CONFIG_CMD_MISC /* Misc functions like sleep etc */
78#define CONFIG_CMD_REGINFO
79#define CONFIG_CMD_RUN /* run command in env variable */
80#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
81#define CONFIG_CMD_XIMG /* Load part of Multi Image */
82
83/*
84 * Autobooting
85 */
86#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
87
88#define CONFIG_PREBOOT "echo;" \
89 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
90 "echo"
91
92#undef CONFIG_BOOTARGS
93/*#define CFG_HUSH_PARSER 0*/
94#ifdef CFG_HUSH_PARSER
95#define CFG_PROMPT_HUSH_PS2 "> "
96#endif
97
98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "netdev=eth0\0" \
100 "nfsargs=setenv bootargs root=/dev/nfs rw " \
101 "nfsroot=${serverip}:${rootpath}\0" \
102 "ramargs=setenv bootargs root=/dev/ram rw\0" \
103 "addip=setenv bootargs ${bootargs} " \
104 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
105 ":${hostname}:${netdev}:off panic=1\0" \
106 "flash_nfs=run nfsargs addip;" \
107 "bootm ${kernel_addr}\0" \
108 "flash_self=run ramargs addip;" \
109 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
110 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
111 "rootpath=/export/roofs\0" \
112 "scratch=40000000\0" \
113 "getkernel=tftpboot \$\(scratch\)\ \$\(bootfile\)\0" \
114 "ethaddr=00:00:7A:CC:00:12\0" \
115 "bootargs=console=ttyS0,38400" \
116 ""
117#define CONFIG_NETMASK 255.255.255.0
118#define CONFIG_GATEWAYIP 192.168.0.1
119#define CONFIG_SERVERIP 192.168.0.81
120#define CONFIG_IPADDR 192.168.0.80
121#define CONFIG_ROOTPATH /export/rootfs
122#define CONFIG_HOSTNAME grxc3s1500
123#define CONFIG_BOOTFILE /uImage
124
125#define CONFIG_BOOTCOMMAND "run flash_self"
126
127/* Memory MAP
128 *
129 * Flash:
130 * |--------------------------------|
131 * | 0x00000000 Text & Data & BSS | *
132 * | for Monitor | *
133 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
134 * | UNUSED / Growth | * 256kb
135 * |--------------------------------|
136 * | 0x00050000 Base custom area | *
137 * | kernel / FS | *
138 * | | * Rest of Flash
139 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
140 * | END-0x00008000 Environment | * 32kb
141 * |--------------------------------|
142 *
143 *
144 *
145 * Main Memory:
146 * |--------------------------------|
147 * | UNUSED / scratch area |
148 * | |
149 * | |
150 * | |
151 * | |
152 * |--------------------------------|
153 * | Monitor .Text / .DATA / .BSS | * 256kb
154 * | Relocated! | *
155 * |--------------------------------|
156 * | Monitor Malloc | * 128kb (contains relocated environment)
157 * |--------------------------------|
158 * | Monitor/kernel STACK | * 64kb
159 * |--------------------------------|
160 * | Page Table for MMU systems | * 2k
161 * |--------------------------------|
162 * | PROM Code accessed from Linux | * 6kb-128b
163 * |--------------------------------|
164 * | Global data (avail from kernel)| * 128b
165 * |--------------------------------|
166 *
167 */
168
169/*
170 * Flash configuration (8,16 or 32 MB)
171 * TEXT base always at 0xFFF00000
172 * ENV_ADDR always at 0xFFF40000
173 * FLASH_BASE at 0xFC000000 for 64 MB
174 * 0xFE000000 for 32 MB
175 * 0xFF000000 for 16 MB
176 * 0xFF800000 for 8 MB
177 */
178#define CFG_NO_FLASH 1
179#define CFG_FLASH_BASE 0x00000000
180#define CFG_FLASH_SIZE 0x00800000
181#define CFG_ENV_SIZE 0x8000
182
183#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_FLASH_SIZE-CFG_ENV_SIZE)
184
185#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
186#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
187#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
188
189#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
190#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
191#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
192#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
193
194#ifdef ENABLE_FLASH_SUPPORT
195/* For use with grsim FLASH emulation extension */
196#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
197
198#undef CONFIG_FLASH_8BIT /* Flash is 32-bit */
199
200/*** CFI CONFIG ***/
201#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200202#define CONFIG_FLASH_CFI_DRIVER
Daniel Hellstrom73caf572008-03-28 10:20:43 +0100203#define CFG_FLASH_CFI
204#endif
205
206/*
207 * Environment settings
208 */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200209#define CONFIG_ENV_IS_NOWHERE 1
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200210/*#define CONFIG_ENV_IS_IN_FLASH*/
Daniel Hellstrom73caf572008-03-28 10:20:43 +0100211/*#define CFG_ENV_SIZE 0x8000*/
212#define CFG_ENV_SECT_SIZE 0x40000
213#define CONFIG_ENV_OVERWRITE 1
214
215/*
216 * Memory map
217 */
218#define CFG_SDRAM_BASE 0x40000000
219#define CFG_SDRAM_SIZE 0x00800000
220#define CFG_SDRAM_END (CFG_SDRAM_BASE+CFG_SDRAM_SIZE)
221
222/* no SRAM available */
223#undef CFG_SRAM_BASE
224#undef CFG_SRAM_SIZE
225
226
227/* Always Run U-Boot from SDRAM */
228#define CFG_RAM_BASE CFG_SDRAM_BASE
229#define CFG_RAM_SIZE CFG_SDRAM_SIZE
230#define CFG_RAM_END CFG_SDRAM_END
231
232#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
233#define CFG_GBL_DATA_OFFSET (CFG_RAM_END - CFG_GBL_DATA_SIZE)
234
235#define CFG_PROM_SIZE (8192-CFG_GBL_DATA_SIZE)
236#define CFG_PROM_OFFSET (CFG_GBL_DATA_OFFSET-CFG_PROM_SIZE)
237
238#define CFG_INIT_SP_OFFSET (CFG_PROM_OFFSET-32)
239#define CFG_STACK_SIZE (0x10000-32)
240
241#define CFG_MONITOR_BASE TEXT_BASE
242#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
243# define CFG_RAMBOOT 1
244#endif
245
246#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
247#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
248#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
249
250#define CFG_MALLOC_END (CFG_INIT_SP_OFFSET-CFG_STACK_SIZE)
251#define CFG_MALLOC_BASE (CFG_MALLOC_END-CFG_MALLOC_LEN)
252
253/* relocated monitor area */
254#define CFG_RELOC_MONITOR_MAX_END CFG_MALLOC_BASE
255#define CFG_RELOC_MONITOR_BASE (CFG_RELOC_MONITOR_MAX_END-CFG_MONITOR_LEN)
256
257/* make un relocated address from relocated address */
258#define UN_RELOC(address) (address-(CFG_RELOC_MONITOR_BASE-TEXT_BASE))
259
260/*
261 * Ethernet configuration
262 */
263/*#define CONFIG_GRETH 1*/
264/*#define CONFIG_NET_MULTI 1*/
265
266/* Default HARDWARE address */
267#define GRETH_HWADDR_0 0x00
268#define GRETH_HWADDR_1 0x00
269#define GRETH_HWADDR_2 0x7A
270#define GRETH_HWADDR_3 0xcc
271#define GRETH_HWADDR_4 0x00
272#define GRETH_HWADDR_5 0x12
273
274#define CONFIG_ETHADDR 00:00:7a:cc:00:12
275
276/*
277 * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
278 */
279/* #define CONFIG_GRETH_10MBIT 1 */
280#define CONFIG_PHY_ADDR 0x00
281
282/*
283 * Miscellaneous configurable options
284 */
285#define CFG_LONGHELP /* undef to save memory */
286#define CFG_PROMPT "=> " /* Monitor Command Prompt */
287#if defined(CONFIG_CMD_KGDB)
288#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
289#else
290#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
291#endif
292#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
293#define CFG_MAXARGS 16 /* max number of command args */
294#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
295
296#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
297#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
298
299#define CFG_LOAD_ADDR 0x100000 /* default load address */
300
301#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
302
303/***** Gaisler GRLIB IP-Cores Config ********/
304
305#define CFG_GRLIB_SDRAM 0
306#define CFG_GRLIB_MEMCFG1 (0x000000ff | (1<<11))
307#if CONFIG_GRSIM
308#define CFG_GRLIB_MEMCFG2 0x82206000
309#else
310#define CFG_GRLIB_MEMCFG2 0x00001820
311#endif
312#define CFG_GRLIB_MEMCFG3 0x00136000
313
314/*** LEON2 UART 1 ***/
315#define CFG_LEON2_UART1_SCALER \
Wolfgang Denk35f734f2008-04-13 09:59:26 -0700316 ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
317
Daniel Hellstrom73caf572008-03-28 10:20:43 +0100318/* UART1 Define to 1 or 0 */
319#define LEON2_UART1_LOOPBACK_ENABLE 0
320#define LEON2_UART1_FLOWCTRL_ENABLE 0
321#define LEON2_UART1_PARITY_ENABLE 0
322#define LEON2_UART1_ODDPAR_ENABLE 0
323
324/*** LEON2 UART 2 ***/
325
326#define CFG_LEON2_UART2_SCALER \
Wolfgang Denk35f734f2008-04-13 09:59:26 -0700327 ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
Daniel Hellstrom73caf572008-03-28 10:20:43 +0100328
329/* UART2 Define to 1 or 0 */
330#define LEON2_UART2_LOOPBACK_ENABLE 0
331#define LEON2_UART2_FLOWCTRL_ENABLE 0
332#define LEON2_UART2_PARITY_ENABLE 0
333#define LEON2_UART2_ODDPAR_ENABLE 0
334
335#define LEON_CONSOLE_UART1 1
336#define LEON_CONSOLE_UART2 2
337
338/* Use UART2 as console */
339#define LEON2_CONSOLE_SELECT LEON_CONSOLE_UART1
340
341/* LEON2 I/O Port */
342/*#define LEON2_IO_PORT_DIR 0x0000aa00*/
343
344/* default kernel command line */
345#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
346
347#define CONFIG_IDENT_STRING "Gaisler GRSIM LEON2"
348
349#endif /* __CONFIG_H */