Simon Glass | 803f6b5 | 2018-12-10 10:37:43 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * max98090.c -- MAX98090 ALSA SoC Audio driver |
| 4 | * |
| 5 | * Copyright 2011 Maxim Integrated Products |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <audio_codec.h> |
| 10 | #include <div64.h> |
| 11 | #include <dm.h> |
| 12 | #include <i2c.h> |
| 13 | #include <i2s.h> |
| 14 | #include <sound.h> |
| 15 | #include <asm/gpio.h> |
Simon Glass | 803f6b5 | 2018-12-10 10:37:43 -0700 | [diff] [blame] | 16 | #include "maxim_codec.h" |
| 17 | #include "max98090.h" |
| 18 | |
| 19 | /* |
| 20 | * Sets hw params for max98090 |
| 21 | * |
| 22 | * @priv: max98090 information pointer |
| 23 | * @rate: Sampling rate |
| 24 | * @bits_per_sample: Bits per sample |
| 25 | * |
| 26 | * @return -EIO for error, 0 for success. |
| 27 | */ |
| 28 | int max98090_hw_params(struct maxim_priv *priv, unsigned int rate, |
| 29 | unsigned int bits_per_sample) |
| 30 | { |
| 31 | int error; |
| 32 | unsigned char value; |
| 33 | |
| 34 | switch (bits_per_sample) { |
| 35 | case 16: |
| 36 | maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value); |
| 37 | error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT, |
| 38 | M98090_WS_MASK, 0); |
| 39 | maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value); |
| 40 | break; |
| 41 | default: |
| 42 | debug("%s: Illegal bits per sample %d.\n", |
| 43 | __func__, bits_per_sample); |
| 44 | return -1; |
| 45 | } |
| 46 | |
| 47 | /* Update filter mode */ |
| 48 | if (rate < 240000) |
| 49 | error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG, |
| 50 | M98090_MODE_MASK, 0); |
| 51 | else |
| 52 | error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG, |
| 53 | M98090_MODE_MASK, M98090_MODE_MASK); |
| 54 | |
| 55 | /* Update sample rate mode */ |
| 56 | if (rate < 50000) |
| 57 | error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG, |
| 58 | M98090_DHF_MASK, 0); |
| 59 | else |
| 60 | error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG, |
| 61 | M98090_DHF_MASK, M98090_DHF_MASK); |
| 62 | |
| 63 | if (error < 0) { |
| 64 | debug("%s: Error setting hardware params.\n", __func__); |
| 65 | return -EIO; |
| 66 | } |
| 67 | priv->rate = rate; |
| 68 | |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * Configures Audio interface system clock for the given frequency |
| 74 | * |
| 75 | * @priv: max98090 information |
| 76 | * @freq: Sampling frequency in Hz |
| 77 | * |
| 78 | * @return -EIO for error, 0 for success. |
| 79 | */ |
| 80 | int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq) |
| 81 | { |
| 82 | int error = 0; |
| 83 | |
| 84 | /* Requested clock frequency is already setup */ |
| 85 | if (freq == priv->sysclk) |
| 86 | return 0; |
| 87 | |
| 88 | /* Setup clocks for slave mode, and using the PLL |
| 89 | * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) |
| 90 | * 0x02 (when master clk is 20MHz to 40MHz).. |
| 91 | * 0x03 (when master clk is 40MHz to 60MHz).. |
| 92 | */ |
| 93 | if (freq >= 10000000 && freq < 20000000) { |
| 94 | error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK, |
| 95 | M98090_PSCLK_DIV1); |
| 96 | } else if (freq >= 20000000 && freq < 40000000) { |
| 97 | error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK, |
| 98 | M98090_PSCLK_DIV2); |
| 99 | } else if (freq >= 40000000 && freq < 60000000) { |
| 100 | error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK, |
| 101 | M98090_PSCLK_DIV4); |
| 102 | } else { |
| 103 | debug("%s: Invalid master clock frequency\n", __func__); |
| 104 | return -1; |
| 105 | } |
| 106 | |
| 107 | debug("%s: Clock at %uHz\n", __func__, freq); |
| 108 | |
| 109 | if (error < 0) |
| 110 | return -1; |
| 111 | |
| 112 | priv->sysclk = freq; |
| 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | /* |
| 118 | * Sets Max98090 I2S format |
| 119 | * |
| 120 | * @priv: max98090 information |
| 121 | * @fmt: i2S format - supports a subset of the options defined in i2s.h. |
| 122 | * |
| 123 | * @return -EIO for error, 0 for success. |
| 124 | */ |
| 125 | int max98090_set_fmt(struct maxim_priv *priv, int fmt) |
| 126 | { |
| 127 | u8 regval = 0; |
| 128 | int error = 0; |
| 129 | |
| 130 | if (fmt == priv->fmt) |
| 131 | return 0; |
| 132 | |
| 133 | priv->fmt = fmt; |
| 134 | |
| 135 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 136 | case SND_SOC_DAIFMT_CBS_CFS: |
| 137 | /* Set to slave mode PLL - MAS mode off */ |
| 138 | error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, |
| 139 | 0x00); |
| 140 | error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, |
| 141 | 0x00); |
| 142 | error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE, |
| 143 | M98090_USE_M1_MASK, 0); |
| 144 | break; |
| 145 | case SND_SOC_DAIFMT_CBM_CFM: |
| 146 | /* Set to master mode */ |
| 147 | debug("Master mode not supported\n"); |
| 148 | break; |
| 149 | case SND_SOC_DAIFMT_CBS_CFM: |
| 150 | case SND_SOC_DAIFMT_CBM_CFS: |
| 151 | default: |
| 152 | debug("%s: Clock mode unsupported\n", __func__); |
| 153 | return -EINVAL; |
| 154 | } |
| 155 | |
| 156 | error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval); |
| 157 | |
| 158 | regval = 0; |
| 159 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 160 | case SND_SOC_DAIFMT_I2S: |
| 161 | regval |= M98090_DLY_MASK; |
| 162 | break; |
| 163 | case SND_SOC_DAIFMT_LEFT_J: |
| 164 | break; |
| 165 | case SND_SOC_DAIFMT_RIGHT_J: |
| 166 | regval |= M98090_RJ_MASK; |
| 167 | break; |
| 168 | case SND_SOC_DAIFMT_DSP_A: |
| 169 | /* Not supported mode */ |
| 170 | default: |
| 171 | debug("%s: Unrecognized format.\n", __func__); |
| 172 | return -EINVAL; |
| 173 | } |
| 174 | |
| 175 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 176 | case SND_SOC_DAIFMT_NB_NF: |
| 177 | break; |
| 178 | case SND_SOC_DAIFMT_NB_IF: |
| 179 | regval |= M98090_WCI_MASK; |
| 180 | break; |
| 181 | case SND_SOC_DAIFMT_IB_NF: |
| 182 | regval |= M98090_BCI_MASK; |
| 183 | break; |
| 184 | case SND_SOC_DAIFMT_IB_IF: |
| 185 | regval |= M98090_BCI_MASK | M98090_WCI_MASK; |
| 186 | break; |
| 187 | default: |
| 188 | debug("%s: Unrecognized inversion settings.\n", __func__); |
| 189 | return -EINVAL; |
| 190 | } |
| 191 | |
| 192 | error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval); |
| 193 | |
| 194 | if (error < 0) { |
| 195 | debug("%s: Error setting i2s format.\n", __func__); |
| 196 | return -EIO; |
| 197 | } |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | /* |
| 203 | * resets the audio codec |
| 204 | * |
| 205 | * @priv: max98090 information |
| 206 | * @return -EIO for error, 0 for success. |
| 207 | */ |
| 208 | static int max98090_reset(struct maxim_priv *priv) |
| 209 | { |
| 210 | int ret; |
| 211 | |
| 212 | /* |
| 213 | * Gracefully reset the DSP core and the codec hardware in a proper |
| 214 | * sequence. |
| 215 | */ |
| 216 | ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET, |
| 217 | M98090_SWRESET_MASK); |
| 218 | if (ret != 0) { |
| 219 | debug("%s: Failed to reset DSP: %d\n", __func__, ret); |
| 220 | return ret; |
| 221 | } |
| 222 | mdelay(20); |
| 223 | |
| 224 | return 0; |
| 225 | } |
| 226 | |
| 227 | /* |
| 228 | * Initialise max98090 codec device |
| 229 | * |
| 230 | * @priv: max98090 information |
| 231 | * |
| 232 | * @return -EIO for error, 0 for success. |
| 233 | */ |
| 234 | int max98090_device_init(struct maxim_priv *priv) |
| 235 | { |
| 236 | unsigned char id; |
| 237 | int error = 0; |
| 238 | |
Simon Glass | 803f6b5 | 2018-12-10 10:37:43 -0700 | [diff] [blame] | 239 | /* reset the codec, the DSP core, and disable all interrupts */ |
| 240 | error = max98090_reset(priv); |
| 241 | if (error != 0) { |
| 242 | debug("Reset\n"); |
| 243 | return error; |
| 244 | } |
| 245 | |
| 246 | /* initialize private data */ |
| 247 | priv->sysclk = -1U; |
| 248 | priv->rate = -1U; |
| 249 | priv->fmt = -1U; |
| 250 | |
| 251 | error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id); |
| 252 | if (error < 0) { |
| 253 | debug("%s: Failure reading hardware revision: %d\n", |
| 254 | __func__, id); |
| 255 | return -EIO; |
| 256 | } |
| 257 | debug("%s: Hardware revision: %d\n", __func__, id); |
| 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | static int max98090_setup_interface(struct maxim_priv *priv) |
| 263 | { |
| 264 | unsigned char id; |
| 265 | int error; |
| 266 | |
| 267 | /* Reading interrupt status to clear them */ |
| 268 | error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id); |
| 269 | |
| 270 | error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL, |
| 271 | M98090_DACHP_MASK); |
| 272 | error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL, |
| 273 | M98090_VCM_MODE_MASK); |
| 274 | |
| 275 | error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1); |
| 276 | error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2); |
| 277 | |
| 278 | error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25); |
| 279 | error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25); |
| 280 | |
| 281 | error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0); |
| 282 | error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0); |
| 283 | error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0); |
| 284 | error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0); |
| 285 | error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION, |
| 286 | M98090_SDIEN_MASK); |
| 287 | error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN, |
| 288 | M98090_SHDNN_MASK); |
| 289 | error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE, |
| 290 | M98090_HPREN_MASK | M98090_HPLEN_MASK | |
| 291 | M98090_SPREN_MASK | M98090_SPLEN_MASK | |
| 292 | M98090_DAREN_MASK | M98090_DALEN_MASK); |
| 293 | error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION, |
| 294 | M98090_SDOEN_MASK | M98090_SDIEN_MASK); |
| 295 | |
| 296 | if (error < 0) |
| 297 | return -EIO; |
| 298 | |
| 299 | return 0; |
| 300 | } |
| 301 | |
| 302 | static int max98090_do_init(struct maxim_priv *priv, int sampling_rate, |
| 303 | int mclk_freq, int bits_per_sample) |
| 304 | { |
| 305 | int ret = 0; |
| 306 | |
| 307 | ret = max98090_setup_interface(priv); |
| 308 | if (ret < 0) { |
| 309 | debug("%s: max98090 setup interface failed\n", __func__); |
| 310 | return ret; |
| 311 | } |
| 312 | |
| 313 | ret = max98090_set_sysclk(priv, mclk_freq); |
| 314 | if (ret < 0) { |
| 315 | debug("%s: max98090 codec set sys clock failed\n", __func__); |
| 316 | return ret; |
| 317 | } |
| 318 | |
| 319 | ret = max98090_hw_params(priv, sampling_rate, bits_per_sample); |
| 320 | |
| 321 | if (ret == 0) { |
| 322 | ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S | |
| 323 | SND_SOC_DAIFMT_NB_NF | |
| 324 | SND_SOC_DAIFMT_CBS_CFS); |
| 325 | } |
| 326 | |
| 327 | return ret; |
| 328 | } |
| 329 | |
| 330 | static int max98090_set_params(struct udevice *dev, int interface, int rate, |
| 331 | int mclk_freq, int bits_per_sample, |
| 332 | uint channels) |
| 333 | { |
| 334 | struct maxim_priv *priv = dev_get_priv(dev); |
| 335 | |
| 336 | return max98090_do_init(priv, rate, mclk_freq, bits_per_sample); |
| 337 | } |
| 338 | |
| 339 | static int max98090_probe(struct udevice *dev) |
| 340 | { |
| 341 | struct maxim_priv *priv = dev_get_priv(dev); |
| 342 | int ret; |
| 343 | |
| 344 | priv->dev = dev; |
| 345 | ret = max98090_device_init(priv); |
| 346 | if (ret < 0) { |
| 347 | debug("%s: max98090 codec chip init failed\n", __func__); |
| 348 | return ret; |
| 349 | } |
| 350 | |
| 351 | return 0; |
| 352 | } |
| 353 | |
| 354 | static const struct audio_codec_ops max98090_ops = { |
| 355 | .set_params = max98090_set_params, |
| 356 | }; |
| 357 | |
| 358 | static const struct udevice_id max98090_ids[] = { |
| 359 | { .compatible = "maxim,max98090" }, |
| 360 | { } |
| 361 | }; |
| 362 | |
| 363 | U_BOOT_DRIVER(max98090) = { |
| 364 | .name = "max98090", |
| 365 | .id = UCLASS_AUDIO_CODEC, |
| 366 | .of_match = max98090_ids, |
| 367 | .probe = max98090_probe, |
| 368 | .ops = &max98090_ops, |
| 369 | .priv_auto_alloc_size = sizeof(struct maxim_priv), |
| 370 | }; |