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git01.mediatek.com / filogic / uboot / 7be97160a526fdc1151adc7cc2ef92de9ba75c6c / . / configs / evb-rk3568_defconfig
blob: cb9b87ff12cb24cb2f3e7d7f204016d384e3aa02 [file] [log] [blame]
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]5CONFIG_TEXT_BASE=0x00a00000
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]6CONFIG_SPL_LIBCOMMON_SUPPORT=y
7CONFIG_SPL_LIBGENERIC_SUPPORT=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]8CONFIG_NR_DRAM_BANKS=2
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]9CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
10CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
Tom Rini5ca768d2022-01-24 21:08:41 +0000[diff] [blame]11CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]12CONFIG_ROCKCHIP_RK3568=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]13CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]14CONFIG_SPL_SERIAL=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]15CONFIG_SPL_STACK_R_ADDR=0x600000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]16CONFIG_SPL_STACK=0x400000
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]17CONFIG_DEBUG_UART_BASE=0xFE660000
18CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]19CONFIG_SYS_LOAD_ADDR=0xc00800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]20CONFIG_DEBUG_UART=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]21CONFIG_FIT=y
22CONFIG_FIT_VERBOSE=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]23CONFIG_SPL_FIT_SIGNATURE=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]24CONFIG_SPL_LOAD_FIT=y
Jonas Karlmanbb5fabe2023-06-26 19:43:06 +0000[diff] [blame]25CONFIG_LEGACY_IMAGE_FORMAT=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]26CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
27# CONFIG_DISPLAY_CPUINFO is not set
28CONFIG_DISPLAY_BOARDINFO_LATE=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]29CONFIG_SPL_MAX_SIZE=0x40000
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]30CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]31CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
32CONFIG_SPL_BSS_START_ADDR=0x4000000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]33CONFIG_SPL_BSS_MAX_SIZE=0x4000
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]34# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]35# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]36CONFIG_SPL_STACK_R=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]37CONFIG_SPL_ATF=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]38CONFIG_CMD_GPIO=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]39CONFIG_CMD_GPT=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]40CONFIG_CMD_I2C=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]41CONFIG_CMD_MMC=y
42# CONFIG_CMD_SETEXPR is not set
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]43CONFIG_CMD_PMIC=y
44CONFIG_CMD_REGULATOR=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]45# CONFIG_SPL_DOS_PARTITION is not set
46CONFIG_SPL_OF_CONTROL=y
47CONFIG_OF_LIVE=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]48CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Jonas Karlmand21f0092023-10-01 19:17:21 +0000[diff] [blame]49CONFIG_SPL_DM_SEQ_ALIAS=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]50CONFIG_SPL_REGMAP=y
51CONFIG_SPL_SYSCON=y
52CONFIG_SPL_CLK=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]53CONFIG_ROCKCHIP_GPIO=y
54CONFIG_SYS_I2C_ROCKCHIP=y
55CONFIG_MISC=y
Tom Rini5df873f2021-12-11 14:55:53 -0500[diff] [blame]56CONFIG_SUPPORT_EMMC_RPMB=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]57CONFIG_MMC_DW=y
58CONFIG_MMC_DW_ROCKCHIP=y
59CONFIG_MMC_SDHCI=y
60CONFIG_MMC_SDHCI_SDMA=y
61CONFIG_MMC_SDHCI_ROCKCHIP=y
Jonas Karlmand21f0092023-10-01 19:17:21 +0000[diff] [blame]62CONFIG_PHY_REALTEK=y
63CONFIG_DWC_ETH_QOS=y
64CONFIG_DWC_ETH_QOS_ROCKCHIP=y
Jonas Karlmanfea31cc2023-05-17 18:26:32 +0000[diff] [blame]65CONFIG_DM_PMIC=y
66CONFIG_PMIC_RK8XX=y
67CONFIG_REGULATOR_RK8XX=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]68CONFIG_PWM_ROCKCHIP=y
Nico Cheng00ceeb02021-10-26 10:42:19 +0800[diff] [blame]69CONFIG_SPL_RAM=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]70CONFIG_BAUDRATE=1500000
71CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]72CONFIG_SYS_NS16550_MEM32=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]73CONFIG_SYSRESET=y
Joseph Chen16899892021-06-02 16:13:46 +0800[diff] [blame]74CONFIG_ERRNO_STR=y