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git01.mediatek.com / filogic / uboot / 7ba3bf61a156710f898c257916dff14f3256951c / . / arch / arm / dts / mt8365-evk.dts
blob: 50cbaefa1a9936c6ff6c3bb7ccb94e7326d4f7a1 [file] [log] [blame]
Julien Masson935b8de2023-12-04 11:48:58 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
14#include "mt8365.dtsi"
15#include "mt6357.dtsi"
16
17/ {
18 model = "MediaTek MT8365 Open Platform EVK";
19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 chosen {
26 stdout-path = "serial0:921600n8";
27 };
28
29 firmware {
30 optee {
31 compatible = "linaro,optee-tz";
32 method = "smc";
33 };
34 };
35
36 gpio-keys {
37 compatible = "gpio-keys";
38 pinctrl-names = "default";
39 pinctrl-0 = <&gpio_keys>;
40
41 key-volume-up {
42 gpios = <&pio 24 GPIO_ACTIVE_LOW>;
43 label = "volume_up";
44 linux,code = <KEY_VOLUMEUP>;
45 wakeup-source;
46 debounce-interval = <15>;
47 };
48 };
49
50 memory@40000000 {
51 device_type = "memory";
52 reg = <0 0x40000000 0 0xc0000000>;
53 };
54
55 usb_otg_vbus: regulator-0 {
56 compatible = "regulator-fixed";
57 regulator-name = "otg_vbus";
58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>;
60 gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
61 enable-active-high;
62 };
63
64 reserved-memory {
65 #address-cells = <2>;
66 #size-cells = <2>;
67 ranges;
68
69 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
70 bl31_secmon_reserved: secmon@43000000 {
71 no-map;
72 reg = <0 0x43000000 0 0x30000>;
73 };
74
75 /* 12 MiB reserved for OP-TEE (BL32)
76 * +-----------------------+ 0x43e0_0000
77 * | SHMEM 2MiB |
78 * +-----------------------+ 0x43c0_0000
79 * | | TA_RAM 8MiB |
80 * + TZDRAM +--------------+ 0x4340_0000
81 * | | TEE_RAM 2MiB |
82 * +-----------------------+ 0x4320_0000
83 */
84 optee_reserved: optee@43200000 {
85 no-map;
86 reg = <0 0x43200000 0 0x00c00000>;
87 };
88 };
89};
90
91&cpu0 {
92 proc-supply = <&mt6357_vproc_reg>;
93 sram-supply = <&mt6357_vsram_proc_reg>;
94};
95
96&cpu1 {
97 proc-supply = <&mt6357_vproc_reg>;
98 sram-supply = <&mt6357_vsram_proc_reg>;
99};
100
101&cpu2 {
102 proc-supply = <&mt6357_vproc_reg>;
103 sram-supply = <&mt6357_vsram_proc_reg>;
104};
105
106&cpu3 {
107 proc-supply = <&mt6357_vproc_reg>;
108 sram-supply = <&mt6357_vsram_proc_reg>;
109};
110
111&ethernet {
112 pinctrl-0 = <&ethernet_pins>;
113 pinctrl-names = "default";
114 phy-handle = <&eth_phy>;
115 phy-mode = "rmii";
116 /*
117 * Ethernet and HDMI (DSI0) are sharing pins.
118 * Only one can be enabled at a time and require the physical switch
119 * SW2101 to be set on LAN position
120 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
121 */
122 status = "disabled";
123
124 mdio {
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 eth_phy: ethernet-phy@0 {
129 reg = <0>;
130 };
131 };
132};
133
134&i2c0 {
135 clock-frequency = <100000>;
136 pinctrl-0 = <&i2c0_pins>;
137 pinctrl-names = "default";
138 status = "okay";
139};
140
141&mmc0 {
142 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
143 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
144 bus-width = <8>;
145 cap-mmc-highspeed;
146 cap-mmc-hw-reset;
147 hs400-ds-delay = <0x12012>;
148 max-frequency = <200000000>;
149 mmc-hs200-1_8v;
150 mmc-hs400-1_8v;
151 no-sd;
152 no-sdio;
153 non-removable;
154 pinctrl-0 = <&mmc0_default_pins>;
155 pinctrl-1 = <&mmc0_uhs_pins>;
156 pinctrl-names = "default", "state_uhs";
157 vmmc-supply = <&mt6357_vemc_reg>;
158 vqmmc-supply = <&mt6357_vio18_reg>;
159 status = "okay";
160};
161
162&mmc1 {
163 bus-width = <4>;
164 cap-sd-highspeed;
165 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
166 max-frequency = <200000000>;
167 pinctrl-0 = <&mmc1_default_pins>;
168 pinctrl-1 = <&mmc1_uhs_pins>;
169 pinctrl-names = "default", "state_uhs";
170 sd-uhs-sdr104;
171 sd-uhs-sdr50;
172 vmmc-supply = <&mt6357_vmch_reg>;
173 vqmmc-supply = <&mt6357_vmc_reg>;
174 status = "okay";
175};
176
177&mt6357_pmic {
178 interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181};
182
183&pio {
184 ethernet_pins: ethernet-pins {
185 phy_reset_pins {
186 pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
187 };
188
189 rmii_pins {
190 pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
191 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
192 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
193 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
194 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
195 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
196 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
197 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
198 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
199 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
200 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
201 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
202 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
203 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
204 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
205 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
206 };
207 };
208
209 gpio_keys: gpio-keys-pins {
210 pins {
211 pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
212 bias-pull-up;
213 input-enable;
214 };
215 };
216
217 i2c0_pins: i2c0-pins {
218 pins {
219 pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
220 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
221 bias-pull-up;
222 };
223 };
224
225 mmc0_default_pins: mmc0-default-pins {
226 clk-pins {
227 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
228 bias-pull-down;
229 };
230
231 cmd-dat-pins {
232 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
233 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
234 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
235 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
236 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
237 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
238 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
239 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
240 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
241 input-enable;
242 bias-pull-up;
243 };
244
245 rst-pins {
246 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
247 bias-pull-up;
248 };
249 };
250
251 mmc0_uhs_pins: mmc0-uhs-pins {
252 clk-pins {
253 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
254 drive-strength = <MTK_DRIVE_10mA>;
255 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
256 };
257
258 cmd-dat-pins {
259 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
260 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
261 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
262 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
263 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
264 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
265 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
266 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
267 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
268 input-enable;
269 drive-strength = <MTK_DRIVE_10mA>;
270 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
271 };
272
273 ds-pins {
274 pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
275 drive-strength = <MTK_DRIVE_10mA>;
276 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
277 };
278
279 rst-pins {
280 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
281 drive-strength = <MTK_DRIVE_10mA>;
282 bias-pull-up;
283 };
284 };
285
286 mmc1_default_pins: mmc1-default-pins {
287 cd-pins {
288 pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
289 bias-pull-up;
290 };
291
292 clk-pins {
293 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
294 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
295 };
296
297 cmd-dat-pins {
298 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
299 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
300 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
301 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
302 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
303 input-enable;
304 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
305 };
306 };
307
308 mmc1_uhs_pins: mmc1-uhs-pins {
309 clk-pins {
310 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
311 drive-strength = <MTK_DRIVE_8mA>;
312 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
313 };
314
315 cmd-dat-pins {
316 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
317 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
318 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
319 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
320 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
321 input-enable;
322 drive-strength = <MTK_DRIVE_6mA>;
323 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
324 };
325 };
326
327 uart0_pins: uart0-pins {
328 pins {
329 pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
330 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
331 };
332 };
333
334 uart1_pins: uart1-pins {
335 pins {
336 pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
337 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
338 };
339 };
340
341 uart2_pins: uart2-pins {
342 pins {
343 pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
344 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
345 };
346 };
347
348 usb_pins: usb-pins {
349 id-pins {
350 pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
351 input-enable;
352 bias-pull-up;
353 };
354
355 usb0-vbus-pins {
356 pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
357 output-high;
358 };
359
360 usb1-vbus-pins {
361 pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
362 output-high;
363 };
364 };
365
366 pwm_pins: pwm-pins {
367 pins {
368 pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
369 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
370 };
371 };
372};
373
374&pwm {
375 pinctrl-0 = <&pwm_pins>;
376 pinctrl-names = "default";
377 status = "okay";
378};
379
380&ssusb {
381 dr_mode = "otg";
382 maximum-speed = "high-speed";
383 pinctrl-0 = <&usb_pins>;
384 pinctrl-names = "default";
385 usb-role-switch;
386 vusb33-supply = <&mt6357_vusb33_reg>;
387 status = "okay";
388
389 connector {
390 compatible = "gpio-usb-b-connector", "usb-b-connector";
391 id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
392 type = "micro";
393 vbus-supply = <&usb_otg_vbus>;
394 };
395};
396
397&usb_host {
398 vusb33-supply = <&mt6357_vusb33_reg>;
399 status = "okay";
400};
401
402&uart0 {
403 pinctrl-0 = <&uart0_pins>;
404 pinctrl-names = "default";
405 status = "okay";
406};
407
408&uart1 {
409 pinctrl-0 = <&uart1_pins>;
410 pinctrl-names = "default";
411 status = "okay";
412};
413
414&uart2 {
415 pinctrl-0 = <&uart2_pins>;
416 pinctrl-names = "default";
417 status = "okay";
418};