Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: BSD-3-Clause AND GPL-2.0 |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 2 | /* |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 3 | * Clock and reset drivers for Qualcomm platforms Global Clock |
| 4 | * Controller (GCC). |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 5 | * |
| 6 | * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 7 | * (C) Copyright 2020 Sartura Ltd. (reset driver) |
| 8 | * Author: Robert Marko <robert.marko@sartura.hr> |
| 9 | * (C) Copyright 2022 Linaro Ltd. (reset driver) |
| 10 | * Author: Sumit Garg <sumit.garg@linaro.org> |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 11 | * |
| 12 | * Based on Little Kernel driver, simplified |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <clk-uclass.h> |
| 17 | #include <dm.h> |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 18 | #include <dm/device-internal.h> |
| 19 | #include <dm/lists.h> |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 20 | #include <errno.h> |
| 21 | #include <asm/io.h> |
| 22 | #include <linux/bitops.h> |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 23 | #include <reset-uclass.h> |
| 24 | |
Caleb Connolly | 878b26a | 2023-11-07 12:40:59 +0000 | [diff] [blame] | 25 | #include "clock-qcom.h" |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 26 | |
| 27 | /* CBCR register fields */ |
| 28 | #define CBCR_BRANCH_ENABLE_BIT BIT(0) |
| 29 | #define CBCR_BRANCH_OFF_BIT BIT(31) |
| 30 | |
| 31 | extern ulong msm_set_rate(struct clk *clk, ulong rate); |
Sumit Garg | 1d1ca6e | 2022-08-04 19:57:14 +0530 | [diff] [blame] | 32 | extern int msm_enable(struct clk *clk); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 33 | |
| 34 | /* Enable clock controlled by CBC soft macro */ |
| 35 | void clk_enable_cbc(phys_addr_t cbcr) |
| 36 | { |
| 37 | setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT); |
| 38 | |
| 39 | while (readl(cbcr) & CBCR_BRANCH_OFF_BIT) |
| 40 | ; |
| 41 | } |
| 42 | |
Ramon Fried | ae29977 | 2018-05-16 12:13:39 +0300 | [diff] [blame] | 43 | void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 44 | { |
| 45 | if (readl(base + gpll0->status) & gpll0->status_bit) |
| 46 | return; /* clock already enabled */ |
| 47 | |
| 48 | setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); |
| 49 | |
| 50 | while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) |
| 51 | ; |
| 52 | } |
| 53 | |
Ramon Fried | ae29977 | 2018-05-16 12:13:39 +0300 | [diff] [blame] | 54 | #define BRANCH_ON_VAL (0) |
| 55 | #define BRANCH_NOC_FSM_ON_VAL BIT(29) |
| 56 | #define BRANCH_CHECK_MASK GENMASK(31, 28) |
| 57 | |
| 58 | void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) |
| 59 | { |
| 60 | u32 val; |
| 61 | |
| 62 | setbits_le32(base + vclk->ena_vote, vclk->vote_bit); |
| 63 | do { |
| 64 | val = readl(base + vclk->cbcr_reg); |
| 65 | val &= BRANCH_CHECK_MASK; |
| 66 | } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); |
| 67 | } |
| 68 | |
Sheep Sun | 49fee7b | 2021-06-20 10:34:35 +0800 | [diff] [blame] | 69 | #define APPS_CMD_RCGR_UPDATE BIT(0) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 70 | |
Sheep Sun | 49fee7b | 2021-06-20 10:34:35 +0800 | [diff] [blame] | 71 | /* Update clock command via CMD_RCGR */ |
| 72 | void clk_bcr_update(phys_addr_t apps_cmd_rcgr) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 73 | { |
Sheep Sun | 49fee7b | 2021-06-20 10:34:35 +0800 | [diff] [blame] | 74 | setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 75 | |
| 76 | /* Wait for frequency to be updated. */ |
Sheep Sun | 49fee7b | 2021-06-20 10:34:35 +0800 | [diff] [blame] | 77 | while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE) |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 78 | ; |
| 79 | } |
| 80 | |
| 81 | #define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */ |
| 82 | |
| 83 | #define CFG_MASK 0x3FFF |
| 84 | |
| 85 | #define CFG_DIVIDER_MASK 0x1F |
| 86 | |
| 87 | /* root set rate for clocks with half integer and MND divider */ |
| 88 | void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, |
| 89 | int div, int m, int n, int source) |
| 90 | { |
| 91 | u32 cfg; |
| 92 | /* M value for MND divider. */ |
| 93 | u32 m_val = m; |
| 94 | /* NOT(N-M) value for MND divider. */ |
| 95 | u32 n_val = ~((n) - (m)) * !!(n); |
| 96 | /* NOT 2D value for MND divider. */ |
| 97 | u32 d_val = ~(n); |
| 98 | |
| 99 | /* Program MND values */ |
| 100 | writel(m_val, base + regs->M); |
| 101 | writel(n_val, base + regs->N); |
| 102 | writel(d_val, base + regs->D); |
| 103 | |
| 104 | /* setup src select and divider */ |
| 105 | cfg = readl(base + regs->cfg_rcgr); |
| 106 | cfg &= ~CFG_MASK; |
| 107 | cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ |
| 108 | |
| 109 | /* Set the divider; HW permits fraction dividers (+0.5), but |
| 110 | for simplicity, we will support integers only */ |
| 111 | if (div) |
| 112 | cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; |
| 113 | |
| 114 | if (n_val) |
| 115 | cfg |= CFG_MODE_DUAL_EDGE; |
| 116 | |
| 117 | writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ |
| 118 | |
| 119 | /* Inform h/w to start using the new config. */ |
| 120 | clk_bcr_update(base + regs->cmd_rcgr); |
| 121 | } |
| 122 | |
Sumit Garg | a3e804d | 2023-02-01 19:28:57 +0530 | [diff] [blame] | 123 | /* root set rate for clocks with half integer and mnd_width=0 */ |
| 124 | void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, |
| 125 | int source) |
| 126 | { |
| 127 | u32 cfg; |
| 128 | |
| 129 | /* setup src select and divider */ |
| 130 | cfg = readl(base + regs->cfg_rcgr); |
| 131 | cfg &= ~CFG_MASK; |
| 132 | cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ |
| 133 | |
| 134 | /* |
| 135 | * Set the divider; HW permits fraction dividers (+0.5), but |
| 136 | * for simplicity, we will support integers only |
| 137 | */ |
| 138 | if (div) |
| 139 | cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; |
| 140 | |
| 141 | writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ |
| 142 | |
| 143 | /* Inform h/w to start using the new config. */ |
| 144 | clk_bcr_update(base + regs->cmd_rcgr); |
| 145 | } |
| 146 | |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 147 | static int msm_clk_probe(struct udevice *dev) |
| 148 | { |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 149 | struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 150 | struct msm_clk_priv *priv = dev_get_priv(dev); |
| 151 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 152 | priv->base = dev_read_addr(dev); |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 153 | if (priv->base == FDT_ADDR_T_NONE) |
| 154 | return -EINVAL; |
| 155 | |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 156 | priv->data = data; |
| 157 | |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | static ulong msm_clk_set_rate(struct clk *clk, ulong rate) |
| 162 | { |
| 163 | return msm_set_rate(clk, rate); |
| 164 | } |
| 165 | |
Sumit Garg | 1d1ca6e | 2022-08-04 19:57:14 +0530 | [diff] [blame] | 166 | static int msm_clk_enable(struct clk *clk) |
| 167 | { |
| 168 | return msm_enable(clk); |
| 169 | } |
| 170 | |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 171 | static struct clk_ops msm_clk_ops = { |
| 172 | .set_rate = msm_clk_set_rate, |
Sumit Garg | 1d1ca6e | 2022-08-04 19:57:14 +0530 | [diff] [blame] | 173 | .enable = msm_clk_enable, |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 174 | }; |
| 175 | |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 176 | U_BOOT_DRIVER(qcom_clk) = { |
| 177 | .name = "qcom_clk", |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 178 | .id = UCLASS_CLK, |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 179 | .ops = &msm_clk_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 180 | .priv_auto = sizeof(struct msm_clk_priv), |
Jorge Ramirez-Ortiz | 92c1eff | 2018-01-10 11:33:49 +0100 | [diff] [blame] | 181 | .probe = msm_clk_probe, |
| 182 | }; |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 183 | |
| 184 | int qcom_cc_bind(struct udevice *parent) |
| 185 | { |
| 186 | struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent); |
| 187 | struct udevice *clkdev, *rstdev; |
| 188 | struct driver *drv; |
| 189 | int ret; |
| 190 | |
| 191 | /* Get a handle to the common clk handler */ |
| 192 | drv = lists_driver_lookup_name("qcom_clk"); |
| 193 | if (!drv) |
| 194 | return -ENOENT; |
| 195 | |
| 196 | /* Register the clock controller */ |
| 197 | ret = device_bind_with_driver_data(parent, drv, "qcom_clk", (ulong)data, |
| 198 | dev_ofnode(parent), &clkdev); |
| 199 | if (ret) |
| 200 | return ret; |
| 201 | |
| 202 | /* Bail out early if resets are not specified for this platform */ |
| 203 | if (!data->resets) |
| 204 | return ret; |
| 205 | |
| 206 | /* Get a handle to the common reset handler */ |
| 207 | drv = lists_driver_lookup_name("qcom_reset"); |
| 208 | if (!drv) |
| 209 | return -ENOENT; |
| 210 | |
| 211 | /* Register the reset controller */ |
| 212 | ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data, |
| 213 | dev_ofnode(parent), &rstdev); |
| 214 | if (ret) |
| 215 | device_unbind(clkdev); |
| 216 | |
| 217 | return ret; |
| 218 | } |
| 219 | |
| 220 | static int qcom_reset_set(struct reset_ctl *rst, bool assert) |
| 221 | { |
| 222 | struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(rst->dev); |
| 223 | void __iomem *base = dev_get_priv(rst->dev); |
| 224 | const struct qcom_reset_map *map; |
| 225 | u32 value; |
| 226 | |
| 227 | map = &data->resets[rst->id]; |
| 228 | |
| 229 | value = readl(base + map->reg); |
| 230 | |
| 231 | if (assert) |
| 232 | value |= BIT(map->bit); |
| 233 | else |
| 234 | value &= ~BIT(map->bit); |
| 235 | |
| 236 | writel(value, base + map->reg); |
| 237 | |
| 238 | return 0; |
| 239 | } |
| 240 | |
| 241 | static int qcom_reset_assert(struct reset_ctl *rst) |
| 242 | { |
| 243 | return qcom_reset_set(rst, true); |
| 244 | } |
| 245 | |
| 246 | static int qcom_reset_deassert(struct reset_ctl *rst) |
| 247 | { |
| 248 | return qcom_reset_set(rst, false); |
| 249 | } |
| 250 | |
| 251 | static const struct reset_ops qcom_reset_ops = { |
| 252 | .rst_assert = qcom_reset_assert, |
| 253 | .rst_deassert = qcom_reset_deassert, |
| 254 | }; |
| 255 | |
| 256 | static int qcom_reset_probe(struct udevice *dev) |
| 257 | { |
| 258 | /* Set our priv pointer to the base address */ |
| 259 | dev_set_priv(dev, (void *)dev_read_addr(dev)); |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | U_BOOT_DRIVER(qcom_reset) = { |
| 265 | .name = "qcom_reset", |
| 266 | .id = UCLASS_RESET, |
| 267 | .ops = &qcom_reset_ops, |
| 268 | .probe = qcom_reset_probe, |
| 269 | }; |