| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Anton Staaf | 49d351b | 2011-10-17 16:46:12 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2011 The Chromium OS Authors. |
| Anton Staaf | 49d351b | 2011-10-17 16:46:12 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __X86_CACHE_H__ |
| 7 | #define __X86_CACHE_H__ |
| 8 | |
| 9 | /* |
| Tom Rini | 3ef67ae | 2021-08-26 11:47:59 -0400 | [diff] [blame] | 10 | * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment. |
| Anton Staaf | 49d351b | 2011-10-17 16:46:12 -0700 | [diff] [blame] | 11 | */ |
| Stefan Roese | 1daf477 | 2016-07-18 12:53:31 +0200 | [diff] [blame] | 12 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 13 | |
| Stefan Reinauer | 2acf848 | 2012-12-02 04:49:50 +0000 | [diff] [blame] | 14 | static inline void wbinvd(void) |
| 15 | { |
| 16 | asm volatile ("wbinvd" : : : "memory"); |
| 17 | } |
| 18 | |
| 19 | static inline void invd(void) |
| 20 | { |
| 21 | asm volatile("invd" : : : "memory"); |
| 22 | } |
| 23 | |
| 24 | /* Enable caches and write buffer */ |
| 25 | void enable_caches(void); |
| 26 | |
| 27 | /* Disable caches and write buffer */ |
| 28 | void disable_caches(void); |
| 29 | |
| Anton Staaf | 49d351b | 2011-10-17 16:46:12 -0700 | [diff] [blame] | 30 | #endif /* __X86_CACHE_H__ */ |