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git01.mediatek.com / filogic / uboot / 79a9da33b05d0f449cf5eafaa606831d56d898fc / . / arch / arm / dts / tegra20.dtsi
blob: a524f6eed4107b669ecc935b247f6b2393bd2629 [file] [log] [blame]
Simon Glass9d3eefd2014-06-11 23:29:52 -0600[diff] [blame]1#include <dt-bindings/gpio/tegra-gpio.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]4#include "skeleton.dtsi"
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]5
6/ {
7 compatible = "nvidia,tegra20";
8 interrupt-parent = <&intc>;
9
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]10 host1x {
11 compatible = "nvidia,tegra20-host1x", "simple-bus";
12 reg = <0x50000000 0x00024000>;
13 interrupts = <0 65 0x04 /* mpcore syncpt */
14 0 67 0x04>; /* mpcore general */
15 status = "disabled";
16
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 ranges = <0x54000000 0x54000000 0x04000000>;
21
22 /* video-encoding/decoding */
23 mpe {
24 reg = <0x54040000 0x00040000>;
25 interrupts = <0 68 0x04>;
26 status = "disabled";
27 };
28
29 /* video input */
30 vi {
31 reg = <0x54080000 0x00040000>;
32 interrupts = <0 69 0x04>;
33 status = "disabled";
34 };
35
36 /* EPP */
37 epp {
38 reg = <0x540c0000 0x00040000>;
39 interrupts = <0 70 0x04>;
40 status = "disabled";
41 };
42
43 /* ISP */
44 isp {
45 reg = <0x54100000 0x00040000>;
46 interrupts = <0 71 0x04>;
47 status = "disabled";
48 };
49
50 /* 2D engine */
51 gr2d {
52 reg = <0x54140000 0x00040000>;
53 interrupts = <0 72 0x04>;
54 status = "disabled";
55 };
56
57 /* 3D engine */
58 gr3d {
59 reg = <0x54180000 0x00040000>;
60 status = "disabled";
61 };
62
63 /* display controllers */
64 dc@54200000 {
65 compatible = "nvidia,tegra20-dc";
66 reg = <0x54200000 0x00040000>;
67 interrupts = <0 73 0x04>;
68 status = "disabled";
69
70 rgb {
71 status = "disabled";
72 };
73 };
74
75 dc@54240000 {
76 compatible = "nvidia,tegra20-dc";
77 reg = <0x54240000 0x00040000>;
78 interrupts = <0 74 0x04>;
79 status = "disabled";
80
81 rgb {
82 status = "disabled";
83 };
84 };
85
86 /* outputs */
87 hdmi {
88 compatible = "nvidia,tegra20-hdmi";
89 reg = <0x54280000 0x00040000>;
90 interrupts = <0 75 0x04>;
91 status = "disabled";
92 };
93
94 tvo {
95 compatible = "nvidia,tegra20-tvo";
96 reg = <0x542c0000 0x00040000>;
97 interrupts = <0 76 0x04>;
98 status = "disabled";
99 };
100
101 dsi {
102 compatible = "nvidia,tegra20-dsi";
103 reg = <0x54300000 0x00040000>;
104 status = "disabled";
105 };
Simon Glass84a64472012-02-27 10:52:43 +0000[diff] [blame]106 };
107
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]108 intc: interrupt-controller@50041000 {
109 compatible = "nvidia,tegra20-gic";
110 interrupt-controller;
111 #interrupt-cells = <1>;
112 reg = < 0x50041000 0x1000 >,
113 < 0x50040100 0x0100 >;
114 };
115
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]116 tegra_car: clock@60006000 {
117 compatible = "nvidia,tegra20-car";
118 reg = <0x60006000 0x1000>;
119 #clock-cells = <1>;
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]120 };
121
Allen Martin3eded042013-01-11 23:07:04 +0000[diff] [blame]122 apbdma: dma {
123 compatible = "nvidia,tegra20-apbdma";
124 reg = <0x6000a000 0x1200>;
125 interrupts = <0 104 0x04
126 0 105 0x04
127 0 106 0x04
128 0 107 0x04
129 0 108 0x04
130 0 109 0x04
131 0 110 0x04
132 0 111 0x04
133 0 112 0x04
134 0 113 0x04
135 0 114 0x04
136 0 115 0x04
137 0 116 0x04
138 0 117 0x04
139 0 118 0x04
140 0 119 0x04>;
141 };
142
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]143 gpio: gpio@6000d000 {
144 compatible = "nvidia,tegra20-gpio";
Simon Glass9d3eefd2014-06-11 23:29:52 -0600[diff] [blame]145 reg = <0x6000d000 0x1000>;
146 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]153 #gpio-cells = <2>;
154 gpio-controller;
Simon Glass9d3eefd2014-06-11 23:29:52 -0600[diff] [blame]155 #interrupt-cells = <2>;
156 interrupt-controller;
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]157 };
158
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]159 pinmux: pinmux@70000000 {
160 compatible = "nvidia,tegra20-pinmux";
161 reg = < 0x70000014 0x10 /* Tri-state registers */
162 0x70000080 0x20 /* Mux registers */
163 0x700000a0 0x14 /* Pull-up/down registers */
164 0x70000868 0xa8 >; /* Pad control registers */
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]165 };
166
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]167 das@70000c00 {
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]168 #address-cells = <1>;
169 #size-cells = <0>;
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]170 compatible = "nvidia,tegra20-das";
171 reg = <0x70000c00 0x80>;
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]172 };
173
174 i2s@70002800 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "nvidia,tegra20-i2s";
178 reg = <0x70002800 0x200>;
179 interrupts = < 45 >;
180 dma-channel = < 2 >;
181 };
182
183 i2s@70002a00 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "nvidia,tegra20-i2s";
187 reg = <0x70002a00 0x200>;
188 interrupts = < 35 >;
189 dma-channel = < 1 >;
190 };
191
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]192 serial@70006000 {
193 compatible = "nvidia,tegra20-uart";
194 reg = <0x70006000 0x40>;
195 reg-shift = <2>;
196 interrupts = < 68 >;
197 };
198
199 serial@70006040 {
200 compatible = "nvidia,tegra20-uart";
201 reg = <0x70006040 0x40>;
202 reg-shift = <2>;
203 interrupts = < 69 >;
204 };
205
206 serial@70006200 {
207 compatible = "nvidia,tegra20-uart";
208 reg = <0x70006200 0x100>;
209 reg-shift = <2>;
210 interrupts = < 78 >;
211 };
212
213 serial@70006300 {
214 compatible = "nvidia,tegra20-uart";
215 reg = <0x70006300 0x100>;
216 reg-shift = <2>;
217 interrupts = < 122 >;
218 };
219
220 serial@70006400 {
221 compatible = "nvidia,tegra20-uart";
222 reg = <0x70006400 0x100>;
223 reg-shift = <2>;
224 interrupts = < 123 >;
225 };
226
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]227 nand: nand-controller@70008000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "nvidia,tegra20-nand";
231 reg = <0x70008000 0x100>;
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]232 };
233
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]234 pwm: pwm@7000a000 {
235 compatible = "nvidia,tegra20-pwm";
236 reg = <0x7000a000 0x100>;
237 #pwm-cells = <2>;
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]238 };
239
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]240 i2c@7000c000 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "nvidia,tegra20-i2c";
244 reg = <0x7000C000 0x100>;
245 interrupts = < 70 >;
246 /* PERIPH_ID_I2C1, PLL_P_OUT3 */
247 clocks = <&tegra_car 12>, <&tegra_car 124>;
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]248 };
249
Allen Martin523e4d62013-01-29 13:51:23 +0000[diff] [blame]250 spi@7000c380 {
251 compatible = "nvidia,tegra20-sflash";
252 reg = <0x7000c380 0x80>;
253 interrupts = <0 39 0x04>;
254 nvidia,dma-request-selector = <&apbdma 11>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 status = "disabled";
258 /* PERIPH_ID_SPI1, PLLP_OUT0 */
259 clocks = <&tegra_car 43>;
260 };
261
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]262 i2c@7000c400 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "nvidia,tegra20-i2c";
266 reg = <0x7000C400 0x100>;
267 interrupts = < 116 >;
268 /* PERIPH_ID_I2C2, PLL_P_OUT3 */
269 clocks = <&tegra_car 54>, <&tegra_car 124>;
270 };
271
272 i2c@7000c500 {
273 #address-cells = <1>;
274 #size-cells = <0>;
275 compatible = "nvidia,tegra20-i2c";
276 reg = <0x7000C500 0x100>;
277 interrupts = < 124 >;
278 /* PERIPH_ID_I2C3, PLL_P_OUT3 */
279 clocks = <&tegra_car 67>, <&tegra_car 124>;
280 };
281
282 i2c@7000d000 {
283 #address-cells = <1>;
284 #size-cells = <0>;
285 compatible = "nvidia,tegra20-i2c-dvc";
286 reg = <0x7000D000 0x200>;
287 interrupts = < 85 >;
288 /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
289 clocks = <&tegra_car 47>, <&tegra_car 124>;
290 };
291
292 kbc@7000e200 {
293 compatible = "nvidia,tegra20-kbc";
294 reg = <0x7000e200 0x0078>;
295 };
296
297 emc@7000f400 {
298 #address-cells = < 1 >;
299 #size-cells = < 0 >;
300 compatible = "nvidia,tegra20-emc";
301 reg = <0x7000f400 0x200>;
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]302 };
303
304 usb@c5000000 {
305 compatible = "nvidia,tegra20-ehci", "usb-ehci";
306 reg = <0xc5000000 0x4000>;
307 interrupts = < 52 >;
308 phy_type = "utmi";
Simon Glass188cbca2012-02-27 10:52:45 +0000[diff] [blame]309 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
310 nvidia,has-legacy-mode;
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]311 };
312
313 usb@c5004000 {
314 compatible = "nvidia,tegra20-ehci", "usb-ehci";
315 reg = <0xc5004000 0x4000>;
316 interrupts = < 53 >;
317 phy_type = "ulpi";
Simon Glass188cbca2012-02-27 10:52:45 +0000[diff] [blame]318 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]319 };
320
321 usb@c5008000 {
322 compatible = "nvidia,tegra20-ehci", "usb-ehci";
323 reg = <0xc5008000 0x4000>;
324 interrupts = < 129 >;
325 phy_type = "utmi";
Simon Glass188cbca2012-02-27 10:52:45 +0000[diff] [blame]326 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]327 };
328
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]329 sdhci@c8000000 {
330 compatible = "nvidia,tegra20-sdhci";
331 reg = <0xc8000000 0x200>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]332 interrupts = <0 14 0x04>;
333 clocks = <&tegra_car 14>;
334 status = "disabled";
Anton Staffd9784872012-04-17 09:01:33 +0000[diff] [blame]335 };
Simon Glass949e53f2012-07-29 20:53:27 +0000[diff] [blame]336
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]337 sdhci@c8000200 {
338 compatible = "nvidia,tegra20-sdhci";
339 reg = <0xc8000200 0x200>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]340 interrupts = <0 15 0x04>;
341 clocks = <&tegra_car 9>;
342 status = "disabled";
Simon Glass949e53f2012-07-29 20:53:27 +0000[diff] [blame]343 };
Simon Glass8b626dc2012-10-17 13:24:47 +0000[diff] [blame]344
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]345 sdhci@c8000400 {
346 compatible = "nvidia,tegra20-sdhci";
347 reg = <0xc8000400 0x200>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]348 interrupts = <0 19 0x04>;
349 clocks = <&tegra_car 69>;
350 status = "disabled";
Simon Glass8b626dc2012-10-17 13:24:47 +0000[diff] [blame]351 };
352
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]353 sdhci@c8000600 {
354 compatible = "nvidia,tegra20-sdhci";
355 reg = <0xc8000600 0x200>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]356 interrupts = <0 31 0x04>;
357 clocks = <&tegra_car 15>;
358 status = "disabled";
Simon Glass3a331e62012-10-17 13:24:48 +0000[diff] [blame]359 };
Simon Glass83aaec82012-02-27 10:52:38 +0000[diff] [blame]360};