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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenkda55c6e2004-01-20 23:12:12 +00002 * (C) Copyright 2000-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite..
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_CRAYL1
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#define CONFIG_405GP 1 /* This is a PPC405 CPU */
38#define CONFIG_4xx 1 /* ...member of PPC405 family */
39#define CONFIG_SYS_CLK_FREQ 25000000
40#define CONFIG_BAUDRATE 9600
41#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
Ben Warren3a918a62008-10-27 23:50:15 -070042
43#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000044#define CONFIG_MII 1 /* MII PHY management */
45#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
wdenkda55c6e2004-01-20 23:12:12 +000046#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */
wdenkc6097192002-11-03 00:24:07 +000047#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
48
49/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
50 * keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
wdenk57b2d802003-06-27 21:31:46 +000051 #define CONFIG_PRAM 16
wdenkc6097192002-11-03 00:24:07 +000052 */
wdenk0893c472003-05-20 14:25:27 +000053#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */
wdenkc6097192002-11-03 00:24:07 +000054#undef CONFIG_BOOTARGS
55
wdenk0893c472003-05-20 14:25:27 +000056/* Bootcmd is overridden by the bootscript in board/cray/L1
wdenkc6097192002-11-03 00:24:07 +000057 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_AUTOLOAD "no"
wdenk0893c472003-05-20 14:25:27 +000059#define CONFIG_BOOTCOMMAND "dhcp"
wdenkc6097192002-11-03 00:24:07 +000060
wdenk57b2d802003-06-27 21:31:46 +000061/*
wdenkc6097192002-11-03 00:24:07 +000062 * ..during experiments..
63 #define CONFIG_SERVERIP 10.0.0.1
wdenk57b2d802003-06-27 21:31:46 +000064 #define CONFIG_ETHADDR 00:40:a6:80:14:5
wdenkc6097192002-11-03 00:24:07 +000065 */
66#define CONFIG_HARD_I2C 1 /* hardware support for i2c */
wdenk0893c472003-05-20 14:25:27 +000067#define CONFIG_SDRAM_BANK0 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
69#define CONFIG_SYS_I2C_SLAVE 0x7F
70#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
71#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenkc6097192002-11-03 00:24:07 +000072#define CONFIG_IDENT_STRING "Cray L1"
73#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
75#define CONFIG_SYS_HUSH_PARSER 1
76#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk0893c472003-05-20 14:25:27 +000077#define CONFIG_AUTOSCRIPT 1
wdenkc6097192002-11-03 00:24:07 +000078
79
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050080/*
81 * Command line configuration.
82 */
83
84#define CONFIG_CMD_BDI
85#define CONFIG_CMD_IMI
86#define CONFIG_CMD_FLASH
87#define CONFIG_CMD_MEMORY
88#define CONFIG_CMD_NET
89#define CONFIG_CMD_ENV
90#define CONFIG_CMD_CONSOLE
91#define CONFIG_CMD_ASKENV
92#define CONFIG_CMD_ECHO
93#define CONFIG_CMD_IMMAP
94#define CONFIG_CMD_REGINFO
95#define CONFIG_CMD_DHCP
96#define CONFIG_CMD_DATE
97#define CONFIG_CMD_RUN
98#define CONFIG_CMD_I2C
99#define CONFIG_CMD_EEPROM
100#define CONFIG_CMD_DIAG
101#define CONFIG_CMD_AUTOSCRIPT
102#define CONFIG_CMD_SETGETDCR
103
wdenkc6097192002-11-03 00:24:07 +0000104
105/*
Jon Loeliger1cb2cb62007-07-09 21:16:53 -0500106 * BOOTP options
wdenkc6097192002-11-03 00:24:07 +0000107 */
Jon Loeliger1cb2cb62007-07-09 21:16:53 -0500108#define CONFIG_BOOTP_SUBNETMASK
109#define CONFIG_BOOTP_GATEWAY
110#define CONFIG_BOOTP_HOSTNAME
111#define CONFIG_BOOTP_BOOTPATH
112#define CONFIG_BOOTP_VENDOREX
113#define CONFIG_BOOTP_DNS
114#define CONFIG_BOOTP_BOOTFILESIZE
115
wdenkc6097192002-11-03 00:24:07 +0000116
wdenk57b2d802003-06-27 21:31:46 +0000117/*
wdenk0893c472003-05-20 14:25:27 +0000118 * how many time to fail & restart a net-TFTP before giving up & resetting
119 * the board hoping that a reset of net interface might help..
120 */
121#define CONFIG_NET_RESET 5
122
wdenk57b2d802003-06-27 21:31:46 +0000123/*
wdenkc6097192002-11-03 00:24:07 +0000124 * bauds. Just to make it compile; in our case, I read the base_baud
125 * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
126 * drives the system clock.
127 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#define CONFIG_SYS_BASE_BAUD 403225
129#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc6097192002-11-03 00:24:07 +0000130 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
131
wdenkc6097192002-11-03 00:24:07 +0000132/*
133 * Miscellaneous configurable options
134 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
136#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
137#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
138#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
139#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
wdenkc6097192002-11-03 00:24:07 +0000140
141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
143#define CONFIG_SYS_TFTP_LOADADDR CONFIG_SYS_LOAD_ADDR
144#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
145#define CONFIG_SYS_DRAM_TEST 1
wdenkc6097192002-11-03 00:24:07 +0000146
147/*-----------------------------------------------------------------------
148 * Start addresses for the final memory configuration
149 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000151 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_SDRAM_BASE 0x00000000
153#define CONFIG_SYS_FLASH_BASE 0xFFC00000
154#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000155
wdenkc6097192002-11-03 00:24:07 +0000156
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
wdenkc6097192002-11-03 00:24:07 +0000158
159/*
160 * For booting Linux, the board info and command line data
161 * have to be in the first 8 MB of memory, since this is
162 * the maximum mapped by the Linux kernel during initialization.
163 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000165/*-----------------------------------------------------------------------
166 * FLASH organization
167 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
169#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
170#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
171#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000172
173/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200174#define CONFIG_ENV_OFFSET 0x3c8000
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200175#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200176#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */
177#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
wdenkc6097192002-11-03 00:24:07 +0000178
wdenk0893c472003-05-20 14:25:27 +0000179/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
wdenkc6097192002-11-03 00:24:07 +0000180 * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
181 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */
183#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
wdenkc6097192002-11-03 00:24:07 +0000184 /* the exception vector table */
185 /* to the end of the DRAM */
186 /* less monitor and malloc area */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
188#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */
189#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
190 + CONFIG_SYS_MALLOC_LEN \
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200191 + CONFIG_ENV_SECT_SIZE \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192 + CONFIG_SYS_STACK_USAGE )
wdenkc6097192002-11-03 00:24:07 +0000193
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
wdenkc6097192002-11-03 00:24:07 +0000195/* END ENVIRONNEMENT FLASH */
196
wdenkc6097192002-11-03 00:24:07 +0000197/*
198 * Init Memory Controller:
199 *
200 * BR0/1 and OR0/1 (FLASH)
201 */
202
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000204
205
206/*-----------------------------------------------------------------------
207 * Definitions for initial stack pointer and data area (in OnChipMem )
208 */
wdenk0893c472003-05-20 14:25:27 +0000209#if 1
210/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_TEMP_STACK_OCM 1
212#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
213#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenk0893c472003-05-20 14:25:27 +0000214
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
216#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
217#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
218#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0893c472003-05-20 14:25:27 +0000220#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
222#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
223#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
224#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of On Chip SRAM */
225#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
226#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
227#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0893c472003-05-20 14:25:27 +0000228#endif
wdenkc6097192002-11-03 00:24:07 +0000229
230/*-----------------------------------------------------------------------
231 * Definitions for Serial Presence Detect EEPROM address
232 */
233#define EEPROM_WRITE_ADDRESS 0xA0
234#define EEPROM_READ_ADDRESS 0xA1
235
236/*
237 * Internal Definitions
238 *
239 * Boot Flags
240 */
241#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
242#define BOOTFLAG_WARM 0x02 /* Software reboot */
243
244#endif /* __CONFIG_H */