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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Dirk Eibachf74a0272014-11-13 19:21:18 +01002/*
3 * (C) Copyright 2014
Mario Sixb4893582018-03-06 08:04:58 +01004 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
Dirk Eibachf74a0272014-11-13 19:21:18 +01005 */
6
7#include <common.h>
8#include <command.h>
9#include <asm/processor.h>
10#include <asm/io.h>
Dirk Eibachf74a0272014-11-13 19:21:18 +010011#include <asm/global_data.h>
12
13#include "mpc8308.h"
14#include <gdsys_fpga.h>
15
16#define REFLECTION_TESTPATTERN 0xdede
17#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
18
19#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
20#define REFLECTION_TESTREG reflection_low
21#else
22#define REFLECTION_TESTREG reflection_high
23#endif
24
25DECLARE_GLOBAL_DATA_PTR;
26
Mario Sixae0feaa2019-03-29 10:18:07 +010027/* as gpio output status cannot be read back, we have to buffer it locally */
28u32 gpio0_out;
29
30void setbits_gpio0_out(u32 mask)
31{
32 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
33
34 gpio0_out |= mask;
35 out_be32(&immr->gpio[0].dat, gpio0_out);
36}
37
38void clrbits_gpio0_out(u32 mask)
39{
40 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
41
42 gpio0_out &= ~mask;
43 out_be32(&immr->gpio[0].dat, gpio0_out);
44}
45
Mario Six3809c472019-03-29 10:18:06 +010046int get_fpga_state(uint dev)
Dirk Eibachf74a0272014-11-13 19:21:18 +010047{
48 return gd->arch.fpga_state[dev];
49}
50
Dirk Eibachf74a0272014-11-13 19:21:18 +010051int board_early_init_f(void)
52{
Mario Six3809c472019-03-29 10:18:06 +010053 uint k;
Dirk Eibachf74a0272014-11-13 19:21:18 +010054
55 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
56 gd->arch.fpga_state[k] = 0;
57
58 return 0;
59}
60
61int board_early_init_r(void)
62{
Mario Six3809c472019-03-29 10:18:06 +010063 uint k;
64 uint ctr;
Dirk Eibachf74a0272014-11-13 19:21:18 +010065
66 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
67 gd->arch.fpga_state[k] = 0;
68
69 /*
70 * reset FPGA
71 */
72 mpc8308_init();
73
74 mpc8308_set_fpga_reset(1);
75
76 mpc8308_setup_hw();
77
78 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
79 ctr = 0;
80 while (!mpc8308_get_fpga_done(k)) {
Mario Six3809c472019-03-29 10:18:06 +010081 mdelay(100);
Dirk Eibachf74a0272014-11-13 19:21:18 +010082 if (ctr++ > 5) {
83 gd->arch.fpga_state[k] |=
84 FPGA_STATE_DONE_FAILED;
85 break;
86 }
87 }
88 }
89
90 udelay(10);
91
92 mpc8308_set_fpga_reset(0);
93
94 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
95 /*
96 * wait for fpga out of reset
97 */
98 ctr = 0;
99 while (1) {
100 u16 val;
101
102 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
103
104 FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
105 if (val == REFLECTION_TESTPATTERN_INV)
106 break;
107
Mario Six3809c472019-03-29 10:18:06 +0100108 mdelay(100);
Dirk Eibachf74a0272014-11-13 19:21:18 +0100109 if (ctr++ > 5) {
110 gd->arch.fpga_state[k] |=
111 FPGA_STATE_REFLECTION_FAILED;
112 break;
113 }
114 }
115 }
116
117 return 0;
118}