Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| 11 | #define CONFIG_405EP 1 /* this is a PPC405 CPU */ |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 12 | #define CONFIG_IOCON 1 /* on a IoCon board */ |
| 13 | |
| 14 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
| 15 | |
| 16 | /* |
| 17 | * Include common defines/options for all AMCC eval boards |
| 18 | */ |
| 19 | #define CONFIG_HOSTNAME iocon |
Dirk Eibach | 2b08d8f | 2014-07-03 09:28:20 +0200 | [diff] [blame] | 20 | #define CONFIG_IDENT_STRING " iocon 0.06" |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 21 | #include "amcc-common.h" |
| 22 | |
Dirk Eibach | 9a65957 | 2012-04-26 03:54:22 +0000 | [diff] [blame] | 23 | #define CONFIG_BOARD_EARLY_INIT_F |
| 24 | #define CONFIG_BOARD_EARLY_INIT_R |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 25 | #define CONFIG_LAST_STAGE_INIT |
| 26 | |
| 27 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
| 28 | |
| 29 | /* |
| 30 | * Configure PLL |
| 31 | */ |
| 32 | #define PLLMR0_DEFAULT PLLMR0_266_133_66 |
| 33 | #define PLLMR1_DEFAULT PLLMR1_266_133_66 |
| 34 | |
Dirk Eibach | 5373c2b | 2012-04-26 03:54:25 +0000 | [diff] [blame] | 35 | #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
Dirk Eibach | 5373c2b | 2012-04-26 03:54:25 +0000 | [diff] [blame] | 36 | |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 37 | /* new uImage format support */ |
| 38 | #define CONFIG_FIT |
| 39 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
Dirk Eibach | 88919ca | 2014-07-03 09:28:26 +0200 | [diff] [blame] | 40 | #define CONFIG_FIT_DISABLE_SHA256 |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 41 | |
| 42 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ |
| 43 | |
| 44 | /* |
| 45 | * Default environment variables |
| 46 | */ |
| 47 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 48 | CONFIG_AMCC_DEF_ENV \ |
| 49 | CONFIG_AMCC_DEF_ENV_POWERPC \ |
| 50 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
| 51 | "kernel_addr=fc000000\0" \ |
| 52 | "fdt_addr=fc1e0000\0" \ |
| 53 | "ramdisk_addr=fc200000\0" \ |
| 54 | "" |
| 55 | |
| 56 | #define CONFIG_PHY_ADDR 4 /* PHY address */ |
| 57 | #define CONFIG_HAS_ETH0 |
| 58 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ |
| 59 | |
| 60 | /* |
| 61 | * Commands additional to the ones defined in amcc-common.h |
| 62 | */ |
| 63 | #define CONFIG_CMD_CACHE |
Michal Simek | eee831a | 2014-06-17 00:36:14 +0200 | [diff] [blame] | 64 | #define CONFIG_CMD_FPGAD |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 65 | #undef CONFIG_CMD_EEPROM |
Dirk Eibach | 6dfe681 | 2014-07-03 09:28:25 +0200 | [diff] [blame] | 66 | #undef CONFIG_CMD_I2C |
| 67 | #undef CONFIG_CMD_IRQ |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * SDRAM configuration (please see cpu/ppc/sdram.[ch]) |
| 71 | */ |
| 72 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
| 73 | |
| 74 | /* SDRAM timings used in datasheet */ |
| 75 | #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ |
| 76 | #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ |
| 77 | #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ |
| 78 | #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ |
| 79 | #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ |
| 80 | |
| 81 | /* |
| 82 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
| 83 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. |
| 84 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. |
| 85 | * The Linux BASE_BAUD define should match this configuration. |
| 86 | * baseBaud = cpuClock/(uartDivisor*16) |
| 87 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
| 88 | * set Linux BASE_BAUD to 403200. |
| 89 | */ |
| 90 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 91 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
| 92 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
| 93 | #define CONFIG_SYS_BASE_BAUD 691200 |
| 94 | |
| 95 | /* |
| 96 | * I2C stuff |
| 97 | */ |
Heiko Schocher | 479a4cf | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 98 | #define CONFIG_SYS_I2C |
Dirk Eibach | 42b204f | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 99 | #define CONFIG_SYS_I2C_PPC4XX |
| 100 | #define CONFIG_SYS_I2C_PPC4XX_CH0 |
| 101 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
| 102 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
Dirk Eibach | b957743 | 2014-07-03 09:28:18 +0200 | [diff] [blame] | 103 | #define CONFIG_SYS_I2C_IHS |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 104 | |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 105 | #define CONFIG_SYS_I2C_SPEED 400000 |
Dirk Eibach | b957743 | 2014-07-03 09:28:18 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_SPD_BUS_NUM 4 |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 107 | |
| 108 | #define CONFIG_PCA953X /* NXP PCA9554 */ |
| 109 | #define CONFIG_PCA9698 /* NXP PCA9698 */ |
| 110 | |
Dirk Eibach | b957743 | 2014-07-03 09:28:18 +0200 | [diff] [blame] | 111 | #define CONFIG_SYS_I2C_IHS_CH0 |
| 112 | #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 |
| 113 | #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F |
| 114 | #define CONFIG_SYS_I2C_IHS_CH1 |
| 115 | #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 |
| 116 | #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F |
| 117 | #define CONFIG_SYS_I2C_IHS_CH2 |
| 118 | #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 |
| 119 | #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F |
| 120 | #define CONFIG_SYS_I2C_IHS_CH3 |
| 121 | #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 |
| 122 | #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F |
| 123 | |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 124 | /* |
| 125 | * Software (bit-bang) I2C driver configuration |
| 126 | */ |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 127 | #define CONFIG_SYS_I2C_SOFT |
| 128 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
| 129 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F |
| 130 | #define I2C_SOFT_DECLARATIONS2 |
| 131 | #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 |
| 132 | #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F |
| 133 | #define I2C_SOFT_DECLARATIONS3 |
| 134 | #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 |
| 135 | #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F |
| 136 | #define I2C_SOFT_DECLARATIONS4 |
| 137 | #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 |
| 138 | #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F |
| 139 | |
Dirk Eibach | b957743 | 2014-07-03 09:28:18 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} |
| 141 | #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} |
| 142 | #define CONFIG_SYS_DP501_I2C {0, 1, 2, 3} |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 143 | |
| 144 | #ifndef __ASSEMBLY__ |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 145 | void fpga_gpio_set(unsigned int bus, int pin); |
| 146 | void fpga_gpio_clear(unsigned int bus, int pin); |
| 147 | int fpga_gpio_get(unsigned int bus, int pin); |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 148 | #endif |
| 149 | |
| 150 | #define I2C_ACTIVE { } |
| 151 | #define I2C_TRISTATE { } |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 152 | #define I2C_READ \ |
| 153 | (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) |
| 154 | #define I2C_SDA(bit) \ |
| 155 | do { \ |
| 156 | if (bit) \ |
| 157 | fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \ |
| 158 | else \ |
| 159 | fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \ |
| 160 | } while (0) |
| 161 | #define I2C_SCL(bit) \ |
| 162 | do { \ |
| 163 | if (bit) \ |
| 164 | fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \ |
| 165 | else \ |
| 166 | fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \ |
| 167 | } while (0) |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 168 | #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ |
| 169 | |
| 170 | /* |
| 171 | * FLASH organization |
| 172 | */ |
| 173 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| 174 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 175 | |
| 176 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 |
| 177 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 178 | |
| 179 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
| 180 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ |
| 181 | |
| 182 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ |
| 183 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ |
| 184 | |
| 185 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 186 | |
| 187 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ |
| 188 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ |
| 189 | |
| 190 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| 191 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
| 192 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
| 193 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
| 194 | |
| 195 | /* Address and size of Redundant Environment Sector */ |
| 196 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 197 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
| 198 | #endif |
| 199 | |
| 200 | /* |
| 201 | * PPC405 GPIO Configuration |
| 202 | */ |
| 203 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ |
| 204 | { \ |
| 205 | /* GPIO Core 0 */ \ |
| 206 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ |
| 207 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ |
| 208 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ |
| 209 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ |
| 210 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ |
| 211 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ |
| 212 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ |
| 213 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ |
| 214 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ |
| 215 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ |
| 216 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ |
| 217 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ |
| 218 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ |
| 219 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ |
| 220 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ |
| 221 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ |
| 222 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ |
| 223 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ |
| 224 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ |
| 225 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ |
| 226 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ |
| 227 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ |
| 228 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ |
| 229 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ |
| 230 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ |
| 231 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ |
| 232 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ |
| 233 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ |
| 234 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ |
| 235 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ |
| 236 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ |
| 237 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ |
| 238 | } \ |
| 239 | } |
| 240 | |
| 241 | /* |
| 242 | * Definitions for initial stack pointer and data area (in data cache) |
| 243 | */ |
| 244 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ |
| 245 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
| 246 | |
| 247 | /* On Chip Memory location */ |
| 248 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 249 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
| 250 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ |
| 251 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ |
| 252 | |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 253 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
Masahiro Yamada | 5854c9f | 2014-02-07 09:23:03 +0900 | [diff] [blame] | 254 | (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 255 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 256 | |
| 257 | /* |
| 258 | * External Bus Controller (EBC) Setup |
| 259 | */ |
| 260 | |
| 261 | /* Memory Bank 0 (NOR-FLASH) initialization */ |
| 262 | #define CONFIG_SYS_EBC_PB0AP 0xa382a880 |
| 263 | #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 |
| 264 | |
| 265 | /* Memory Bank 1 (NVRAM) initializatio */ |
| 266 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
| 267 | #define CONFIG_SYS_EBC_PB1CR 0xFB858000 |
| 268 | |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 269 | /* Memory Bank 2 (FPGA0) initialization */ |
| 270 | #define CONFIG_SYS_FPGA0_BASE 0x7f100000 |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 271 | #define CONFIG_SYS_EBC_PB2AP 0x02825080 |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 272 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000) |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 273 | |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 274 | #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE |
| 275 | #define CONFIG_SYS_FPGA_DONE(k) 0x0010 |
| 276 | |
| 277 | #define CONFIG_SYS_FPGA_COUNT 1 |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 278 | |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 279 | #define CONFIG_SYS_MCLINK_MAX 3 |
Dirk Eibach | 20614a2 | 2013-06-26 16:04:26 +0200 | [diff] [blame] | 280 | |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 281 | #define CONFIG_SYS_FPGA_PTR \ |
| 282 | { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } |
Dirk Eibach | 20614a2 | 2013-06-26 16:04:26 +0200 | [diff] [blame] | 283 | |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 284 | /* Memory Bank 3 (Latches) initialization */ |
| 285 | #define CONFIG_SYS_LATCH_BASE 0x7f200000 |
| 286 | #define CONFIG_SYS_EBC_PB3AP 0x02025080 |
| 287 | #define CONFIG_SYS_EBC_PB3CR 0x7f21a000 |
| 288 | |
| 289 | #define CONFIG_SYS_LATCH0_RESET 0xffef |
| 290 | #define CONFIG_SYS_LATCH0_BOOT 0xffff |
| 291 | #define CONFIG_SYS_LATCH1_RESET 0xffff |
| 292 | #define CONFIG_SYS_LATCH1_BOOT 0xffff |
| 293 | |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 294 | /* |
| 295 | * OSD Setup |
| 296 | */ |
| 297 | #define CONFIG_SYS_MPC92469AC |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 298 | #define CONFIG_SYS_OSD_SCREENS 1 |
Dirk Eibach | 4a3eae1 | 2014-07-03 09:28:17 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_DP501_DIFFERENTIAL |
| 300 | #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ |
Dirk Eibach | 437145e | 2013-07-25 19:28:13 +0200 | [diff] [blame] | 301 | |
| 302 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
| 303 | #define CONFIG_BITBANGMII_MULTI |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 304 | |
Dirk Eibach | 9a13d81 | 2010-10-21 10:50:05 +0200 | [diff] [blame] | 305 | #endif /* __CONFIG_H */ |