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git01.mediatek.com / filogic / uboot / 77d8dc6f431d2dae242818b74dfb0eea7287984e / . / configs / at91sam9rlek_mmc_defconfig
blob: 70d431c1f5202164de75a9825dab0545657e2b08 [file] [log] [blame]
Wu, Josh7ff194f2015-02-02 17:51:01 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]3CONFIG_ARCH_CPU_INIT=y
Tom Rini340fcdb2015-03-20 10:47:38 -0400[diff] [blame]4CONFIG_ARCH_AT91=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]5CONFIG_TEXT_BASE=0x21F00000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]6CONFIG_SYS_MALLOC_LEN=0x2c000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]7CONFIG_TARGET_AT91SAM9RLEK=y
Tom Rini201e75e2022-03-11 23:07:36 -0500[diff] [blame]8CONFIG_ATMEL_LEGACY=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]9CONFIG_NR_DRAM_BANKS=1
Markus Klotzbuecher7bd60e62019-05-15 15:15:54 +0200[diff] [blame]10CONFIG_ENV_SIZE=0x4000
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]11CONFIG_DM_GPIO=y
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]12CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]13CONFIG_DEBUG_UART_BASE=0xfffff200
14CONFIG_DEBUG_UART_CLOCK=100000000
Tom Rini7c027e02022-06-20 08:13:12 -0400[diff] [blame]15CONFIG_DEBUG_UART_BOARD_INIT=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]16CONFIG_SYS_LOAD_ADDR=0x22000000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]17CONFIG_DEBUG_UART=y
Tom Rini9ec25872022-03-24 17:18:03 -0400[diff] [blame]18CONFIG_SD_BOOT=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]19CONFIG_BOOTDELAY=3
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]20CONFIG_USE_BOOTARGS=y
21CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootwait"
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]22CONFIG_USE_BOOTCOMMAND=y
23CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
Tom Rini914a8c02024-01-03 09:26:16 -0500[diff] [blame]24CONFIG_SYS_CBSIZE=256
25CONFIG_SYS_PBSIZE=281
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]26CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]27# CONFIG_DISPLAY_BOARDINFO is not set
Wu, Josha9b5d1a2015-02-03 18:19:05 +0800[diff] [blame]28CONFIG_HUSH_PARSER=y
Tom Rinic4359852023-10-02 10:35:27 -0400[diff] [blame]29CONFIG_SYS_PROMPT="U-Boot> "
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]30# CONFIG_CMD_BDI is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]31CONFIG_CMD_BOOTZ=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]32# CONFIG_CMD_IMI is not set
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]33# CONFIG_CMD_LOADS is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]34CONFIG_CMD_MMC=y
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]35CONFIG_CMD_NAND=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]36# CONFIG_CMD_SOURCE is not set
37# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]38CONFIG_CMD_FAT=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]39CONFIG_OF_CONTROL=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]40CONFIG_ENV_IS_IN_FAT=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]41CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Michal Simek2f785a12018-02-26 16:01:02 +0100[diff] [blame]42# CONFIG_NET is not set
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]43CONFIG_CLK=y
44CONFIG_CLK_AT91=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]45CONFIG_AT91_GPIO=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]46CONFIG_GENERIC_ATMEL_MCI=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]47CONFIG_MTD=y
Miquel Raynald0935362019-10-03 19:50:03 +0200[diff] [blame]48CONFIG_MTD_RAW_NAND=y
Adam Ford9c519182018-07-08 08:11:07 -0500[diff] [blame]49CONFIG_NAND_ATMEL=y
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +0800[diff] [blame]50CONFIG_DM_SPI_FLASH=y
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +0800[diff] [blame]51CONFIG_SPI_FLASH_ATMEL=y
52CONFIG_SPI_FLASH_DATAFLASH=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]53CONFIG_PINCTRL=y
54CONFIG_PINCTRL_AT91=y
55CONFIG_DM_SERIAL=y
Wenyou Yangde5793e2017-04-18 15:28:29 +0800[diff] [blame]56CONFIG_DEBUG_UART_ANNOUNCE=y
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]57CONFIG_ATMEL_USART=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]58CONFIG_SPI=y
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +0800[diff] [blame]59CONFIG_DM_SPI=y
Wenyou.Yang@microchip.com272167d2017-08-15 17:40:27 +0800[diff] [blame]60CONFIG_TIMER=y
61CONFIG_ATMEL_PIT_TIMER=y