Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007 |
| 4 | * Sascha Hauer, Pengutronix |
| 5 | * |
| 6 | * (C) Copyright 2009 Freescale Semiconductor, Inc. |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 11 | #include <linux/delay.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 12 | #include <linux/errno.h> |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 13 | #include <asm/io.h> |
| 14 | #include <asm/arch/imx-regs.h> |
| 15 | #include <asm/arch/clock.h> |
| 16 | #include <asm/arch/sys_proto.h> |
Diego Dorta | 3a5bf53 | 2017-09-27 13:12:37 -0300 | [diff] [blame] | 17 | #include <asm/bootm.h> |
Stefano Babic | 33731bc | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 18 | #include <asm/mach-imx/boot_mode.h> |
| 19 | #include <asm/mach-imx/dma.h> |
| 20 | #include <asm/mach-imx/hab.h> |
Fabio Estevam | 48e65b0 | 2013-02-07 06:45:23 +0000 | [diff] [blame] | 21 | #include <stdbool.h> |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 22 | #include <asm/arch/mxc_hdmi.h> |
| 23 | #include <asm/arch/crm_regs.h> |
Ye.Li | f19692c | 2014-11-20 21:14:14 +0800 | [diff] [blame] | 24 | #include <dm.h> |
Heinrich Schuchardt | cdd0c85 | 2020-06-26 19:57:55 +0200 | [diff] [blame] | 25 | #include <fsl_sec.h> |
Ye.Li | f19692c | 2014-11-20 21:14:14 +0800 | [diff] [blame] | 26 | #include <imx_thermal.h> |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 27 | #include <mmc.h> |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 28 | |
Jorge Ramirez-Ortiz | 76d9539 | 2020-10-23 21:18:41 +0200 | [diff] [blame^] | 29 | #define has_err007805() \ |
| 30 | (is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull()) |
| 31 | |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 32 | struct scu_regs { |
| 33 | u32 ctrl; |
| 34 | u32 config; |
| 35 | u32 status; |
| 36 | u32 invalidate; |
| 37 | u32 fpga_rev; |
| 38 | }; |
| 39 | |
Simon Glass | 8c19f7b | 2020-10-29 11:08:25 -0600 | [diff] [blame] | 40 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL) |
Ye.Li | f19692c | 2014-11-20 21:14:14 +0800 | [diff] [blame] | 41 | static const struct imx_thermal_plat imx6_thermal_plat = { |
| 42 | .regs = (void *)ANATOP_BASE_ADDR, |
| 43 | .fuse_bank = 1, |
| 44 | .fuse_word = 6, |
| 45 | }; |
| 46 | |
| 47 | U_BOOT_DEVICE(imx6_thermal) = { |
| 48 | .name = "imx_thermal", |
| 49 | .platdata = &imx6_thermal_plat, |
| 50 | }; |
| 51 | #endif |
| 52 | |
Stefano Babic | f8b509b | 2019-09-20 08:47:53 +0200 | [diff] [blame] | 53 | #if defined(CONFIG_IMX_HAB) |
Adrian Alonso | 6ec8d84 | 2015-10-12 13:48:12 -0500 | [diff] [blame] | 54 | struct imx_sec_config_fuse_t const imx_sec_config_fuse = { |
| 55 | .bank = 0, |
| 56 | .word = 6, |
| 57 | }; |
| 58 | #endif |
| 59 | |
Gabriel Huau | 170ceaf | 2014-07-26 11:35:43 -0700 | [diff] [blame] | 60 | u32 get_nr_cpus(void) |
| 61 | { |
| 62 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; |
| 63 | return readl(&scu->config) & 3; |
| 64 | } |
| 65 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 66 | u32 get_cpu_rev(void) |
| 67 | { |
Fabio Estevam | 46e9733 | 2012-03-20 04:21:45 +0000 | [diff] [blame] | 68 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 69 | u32 reg = readl(&anatop->digprog_sololite); |
| 70 | u32 type = ((reg >> 16) & 0xff); |
Peng Fan | 5f24792 | 2015-07-11 11:38:42 +0800 | [diff] [blame] | 71 | u32 major, cfg = 0; |
Fabio Estevam | 46e9733 | 2012-03-20 04:21:45 +0000 | [diff] [blame] | 72 | |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 73 | if (type != MXC_CPU_MX6SL) { |
| 74 | reg = readl(&anatop->digprog); |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 75 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; |
Peng Fan | 5f24792 | 2015-07-11 11:38:42 +0800 | [diff] [blame] | 76 | cfg = readl(&scu->config) & 3; |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 77 | type = ((reg >> 16) & 0xff); |
| 78 | if (type == MXC_CPU_MX6DL) { |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 79 | if (!cfg) |
| 80 | type = MXC_CPU_MX6SOLO; |
| 81 | } |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 82 | |
| 83 | if (type == MXC_CPU_MX6Q) { |
| 84 | if (cfg == 1) |
| 85 | type = MXC_CPU_MX6D; |
| 86 | } |
| 87 | |
Peng Fan | c53d0c9 | 2019-08-08 09:55:52 +0000 | [diff] [blame] | 88 | if (type == MXC_CPU_MX6ULL) { |
| 89 | if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6)) |
| 90 | type = MXC_CPU_MX6ULZ; |
| 91 | } |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 92 | } |
Peng Fan | 8838323 | 2015-06-11 18:30:36 +0800 | [diff] [blame] | 93 | major = ((reg >> 8) & 0xff); |
Peng Fan | 5f24792 | 2015-07-11 11:38:42 +0800 | [diff] [blame] | 94 | if ((major >= 1) && |
| 95 | ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { |
| 96 | major--; |
| 97 | type = MXC_CPU_MX6QP; |
| 98 | if (cfg == 1) |
| 99 | type = MXC_CPU_MX6DP; |
| 100 | } |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 101 | reg &= 0xff; /* mx6 silicon revision */ |
Ye Li | 10f19c7 | 2019-07-10 10:38:37 +0000 | [diff] [blame] | 102 | |
| 103 | /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/ |
| 104 | if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5)) |
| 105 | reg = 0x3; |
| 106 | |
Peng Fan | 8838323 | 2015-06-11 18:30:36 +0800 | [diff] [blame] | 107 | return (type << 12) | (reg + (0x10 * (major + 1))); |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 108 | } |
| 109 | |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 110 | /* |
| 111 | * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440) |
| 112 | * defines a 2-bit SPEED_GRADING |
| 113 | */ |
| 114 | #define OCOTP_CFG3_SPEED_SHIFT 16 |
| 115 | #define OCOTP_CFG3_SPEED_800MHZ 0 |
| 116 | #define OCOTP_CFG3_SPEED_850MHZ 1 |
| 117 | #define OCOTP_CFG3_SPEED_1GHZ 2 |
| 118 | #define OCOTP_CFG3_SPEED_1P2GHZ 3 |
| 119 | |
Peng Fan | 441e905 | 2016-05-03 11:13:04 +0800 | [diff] [blame] | 120 | /* |
| 121 | * For i.MX6UL |
| 122 | */ |
| 123 | #define OCOTP_CFG3_SPEED_528MHZ 1 |
| 124 | #define OCOTP_CFG3_SPEED_696MHZ 2 |
| 125 | |
Sébastien Szymanski | b130c8a | 2017-08-02 17:05:27 +0200 | [diff] [blame] | 126 | /* |
| 127 | * For i.MX6ULL |
| 128 | */ |
| 129 | #define OCOTP_CFG3_SPEED_792MHZ 2 |
| 130 | #define OCOTP_CFG3_SPEED_900MHZ 3 |
| 131 | |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 132 | u32 get_cpu_speed_grade_hz(void) |
| 133 | { |
| 134 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 135 | struct fuse_bank *bank = &ocotp->bank[0]; |
| 136 | struct fuse_bank0_regs *fuse = |
| 137 | (struct fuse_bank0_regs *)bank->fuse_regs; |
| 138 | uint32_t val; |
| 139 | |
| 140 | val = readl(&fuse->cfg3); |
| 141 | val >>= OCOTP_CFG3_SPEED_SHIFT; |
| 142 | val &= 0x3; |
| 143 | |
Sébastien Szymanski | b130c8a | 2017-08-02 17:05:27 +0200 | [diff] [blame] | 144 | if (is_mx6ul()) { |
Peng Fan | 441e905 | 2016-05-03 11:13:04 +0800 | [diff] [blame] | 145 | if (val == OCOTP_CFG3_SPEED_528MHZ) |
| 146 | return 528000000; |
| 147 | else if (val == OCOTP_CFG3_SPEED_696MHZ) |
Sébastien Szymanski | 415c7ce | 2017-08-02 17:05:26 +0200 | [diff] [blame] | 148 | return 696000000; |
Peng Fan | 441e905 | 2016-05-03 11:13:04 +0800 | [diff] [blame] | 149 | else |
| 150 | return 0; |
| 151 | } |
| 152 | |
Sébastien Szymanski | b130c8a | 2017-08-02 17:05:27 +0200 | [diff] [blame] | 153 | if (is_mx6ull()) { |
| 154 | if (val == OCOTP_CFG3_SPEED_528MHZ) |
| 155 | return 528000000; |
| 156 | else if (val == OCOTP_CFG3_SPEED_792MHZ) |
| 157 | return 792000000; |
| 158 | else if (val == OCOTP_CFG3_SPEED_900MHZ) |
| 159 | return 900000000; |
| 160 | else |
| 161 | return 0; |
| 162 | } |
| 163 | |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 164 | switch (val) { |
| 165 | /* Valid for IMX6DQ */ |
| 166 | case OCOTP_CFG3_SPEED_1P2GHZ: |
Peng Fan | 6c4f76f | 2016-05-23 18:35:58 +0800 | [diff] [blame] | 167 | if (is_mx6dq() || is_mx6dqp()) |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 168 | return 1200000000; |
| 169 | /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ |
| 170 | case OCOTP_CFG3_SPEED_1GHZ: |
| 171 | return 996000000; |
| 172 | /* Valid for IMX6DQ */ |
| 173 | case OCOTP_CFG3_SPEED_850MHZ: |
Peng Fan | 6c4f76f | 2016-05-23 18:35:58 +0800 | [diff] [blame] | 174 | if (is_mx6dq() || is_mx6dqp()) |
Tim Harvey | 258d046 | 2015-05-18 07:02:24 -0700 | [diff] [blame] | 175 | return 852000000; |
| 176 | /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ |
| 177 | case OCOTP_CFG3_SPEED_800MHZ: |
| 178 | return 792000000; |
| 179 | } |
| 180 | return 0; |
| 181 | } |
| 182 | |
Tim Harvey | 5e0e193 | 2015-05-18 06:56:45 -0700 | [diff] [blame] | 183 | /* |
| 184 | * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480) |
| 185 | * defines a 2-bit Temperature Grade |
| 186 | * |
Fabio Estevam | a24859c | 2017-06-22 10:50:05 -0300 | [diff] [blame] | 187 | * return temperature grade and min/max temperature in Celsius |
Tim Harvey | 5e0e193 | 2015-05-18 06:56:45 -0700 | [diff] [blame] | 188 | */ |
| 189 | #define OCOTP_MEM0_TEMP_SHIFT 6 |
| 190 | |
| 191 | u32 get_cpu_temp_grade(int *minc, int *maxc) |
| 192 | { |
| 193 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 194 | struct fuse_bank *bank = &ocotp->bank[1]; |
| 195 | struct fuse_bank1_regs *fuse = |
| 196 | (struct fuse_bank1_regs *)bank->fuse_regs; |
| 197 | uint32_t val; |
| 198 | |
| 199 | val = readl(&fuse->mem0); |
| 200 | val >>= OCOTP_MEM0_TEMP_SHIFT; |
| 201 | val &= 0x3; |
| 202 | |
| 203 | if (minc && maxc) { |
| 204 | if (val == TEMP_AUTOMOTIVE) { |
| 205 | *minc = -40; |
| 206 | *maxc = 125; |
| 207 | } else if (val == TEMP_INDUSTRIAL) { |
| 208 | *minc = -40; |
| 209 | *maxc = 105; |
| 210 | } else if (val == TEMP_EXTCOMMERCIAL) { |
| 211 | *minc = -20; |
| 212 | *maxc = 105; |
| 213 | } else { |
| 214 | *minc = 0; |
| 215 | *maxc = 95; |
| 216 | } |
| 217 | } |
| 218 | return val; |
| 219 | } |
| 220 | |
Fabio Estevam | 435998b | 2013-03-27 07:36:55 +0000 | [diff] [blame] | 221 | #ifdef CONFIG_REVISION_TAG |
| 222 | u32 __weak get_board_rev(void) |
| 223 | { |
| 224 | u32 cpurev = get_cpu_rev(); |
| 225 | u32 type = ((cpurev >> 12) & 0xff); |
| 226 | if (type == MXC_CPU_MX6SOLO) |
| 227 | cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); |
| 228 | |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 229 | if (type == MXC_CPU_MX6D) |
| 230 | cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); |
| 231 | |
Fabio Estevam | 435998b | 2013-03-27 07:36:55 +0000 | [diff] [blame] | 232 | return cpurev; |
| 233 | } |
| 234 | #endif |
| 235 | |
Fabio Estevam | cf621ff | 2013-12-26 14:51:31 -0200 | [diff] [blame] | 236 | static void clear_ldo_ramp(void) |
| 237 | { |
| 238 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
| 239 | int reg; |
| 240 | |
| 241 | /* ROM may modify LDO ramp up time according to fuse setting, so in |
| 242 | * order to be in the safe side we neeed to reset these settings to |
| 243 | * match the reset value: 0'b00 |
| 244 | */ |
| 245 | reg = readl(&anatop->ana_misc2); |
| 246 | reg &= ~(0x3f << 24); |
| 247 | writel(reg, &anatop->ana_misc2); |
| 248 | } |
| 249 | |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 250 | /* |
Fabio Estevam | 2e95fe1 | 2014-06-13 01:42:37 -0300 | [diff] [blame] | 251 | * Set the PMU_REG_CORE register |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 252 | * |
Fabio Estevam | 2e95fe1 | 2014-06-13 01:42:37 -0300 | [diff] [blame] | 253 | * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 254 | * Possible values are from 0.725V to 1.450V in steps of |
| 255 | * 0.025V (25mV). |
| 256 | */ |
Marek Vasut | 02fec41 | 2019-11-26 09:35:32 +0100 | [diff] [blame] | 257 | int set_ldo_voltage(enum ldo_reg ldo, u32 mv) |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 258 | { |
| 259 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 260 | u32 val, step, old, reg = readl(&anatop->reg_core); |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 261 | u8 shift; |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 262 | |
Peng Fan | 81224c4 | 2017-08-08 16:21:35 +0800 | [diff] [blame] | 263 | /* No LDO_SOC/PU/ARM */ |
| 264 | if (is_mx6sll()) |
| 265 | return 0; |
| 266 | |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 267 | if (mv < 725) |
| 268 | val = 0x00; /* Power gated off */ |
| 269 | else if (mv > 1450) |
| 270 | val = 0x1F; /* Power FET switched full on. No regulation */ |
| 271 | else |
| 272 | val = (mv - 700) / 25; |
| 273 | |
Fabio Estevam | cf621ff | 2013-12-26 14:51:31 -0200 | [diff] [blame] | 274 | clear_ldo_ramp(); |
| 275 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 276 | switch (ldo) { |
| 277 | case LDO_SOC: |
| 278 | shift = 18; |
| 279 | break; |
| 280 | case LDO_PU: |
| 281 | shift = 9; |
| 282 | break; |
| 283 | case LDO_ARM: |
| 284 | shift = 0; |
| 285 | break; |
| 286 | default: |
| 287 | return -EINVAL; |
| 288 | } |
| 289 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 290 | old = (reg & (0x1F << shift)) >> shift; |
| 291 | step = abs(val - old); |
| 292 | if (step == 0) |
| 293 | return 0; |
| 294 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 295 | reg = (reg & ~(0x1F << shift)) | (val << shift); |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 296 | writel(reg, &anatop->reg_core); |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 297 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 298 | /* |
| 299 | * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per |
| 300 | * step |
| 301 | */ |
| 302 | udelay(3 * step); |
| 303 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 304 | return 0; |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 305 | } |
| 306 | |
Anson Huang | 05a464f | 2014-01-23 14:00:18 +0800 | [diff] [blame] | 307 | static void set_ahb_rate(u32 val) |
| 308 | { |
| 309 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 310 | u32 reg, div; |
| 311 | |
| 312 | div = get_periph_clk() / val - 1; |
| 313 | reg = readl(&mxc_ccm->cbcdr); |
| 314 | |
| 315 | writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | |
| 316 | (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); |
| 317 | } |
| 318 | |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 319 | static void clear_mmdc_ch_mask(void) |
| 320 | { |
| 321 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
Peng Fan | 53f3c9e | 2015-07-11 11:38:43 +0800 | [diff] [blame] | 322 | u32 reg; |
| 323 | reg = readl(&mxc_ccm->ccdr); |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 324 | |
| 325 | /* Clear MMDC channel mask */ |
Peng Fan | 81224c4 | 2017-08-08 16:21:35 +0800 | [diff] [blame] | 326 | if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll()) |
Ye Li | 64cef44 | 2016-03-09 16:13:48 +0800 | [diff] [blame] | 327 | reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); |
| 328 | else |
| 329 | reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); |
Peng Fan | 53f3c9e | 2015-07-11 11:38:43 +0800 | [diff] [blame] | 330 | writel(reg, &mxc_ccm->ccdr); |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 331 | } |
| 332 | |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 333 | #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8 |
| 334 | |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 335 | static void init_bandgap(void) |
| 336 | { |
| 337 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 338 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 339 | struct fuse_bank *bank = &ocotp->bank[1]; |
| 340 | struct fuse_bank1_regs *fuse = |
| 341 | (struct fuse_bank1_regs *)bank->fuse_regs; |
| 342 | uint32_t val; |
| 343 | |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 344 | /* |
| 345 | * Ensure the bandgap has stabilized. |
| 346 | */ |
| 347 | while (!(readl(&anatop->ana_misc0) & 0x80)) |
| 348 | ; |
| 349 | /* |
| 350 | * For best noise performance of the analog blocks using the |
| 351 | * outputs of the bandgap, the reftop_selfbiasoff bit should |
| 352 | * be set. |
| 353 | */ |
| 354 | writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); |
Peng Fan | 6b98935 | 2016-08-11 14:02:50 +0800 | [diff] [blame] | 355 | /* |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 356 | * On i.MX6ULL,we need to set VBGADJ bits according to the |
| 357 | * REFTOP_TRIM[3:0] in fuse table |
| 358 | * 000 - set REFTOP_VBGADJ[2:0] to 3b'110, |
| 359 | * 110 - set REFTOP_VBGADJ[2:0] to 3b'000, |
| 360 | * 001 - set REFTOP_VBGADJ[2:0] to 3b'001, |
| 361 | * 010 - set REFTOP_VBGADJ[2:0] to 3b'010, |
| 362 | * 011 - set REFTOP_VBGADJ[2:0] to 3b'011, |
| 363 | * 100 - set REFTOP_VBGADJ[2:0] to 3b'100, |
| 364 | * 101 - set REFTOP_VBGADJ[2:0] to 3b'101, |
| 365 | * 111 - set REFTOP_VBGADJ[2:0] to 3b'111, |
Peng Fan | 6b98935 | 2016-08-11 14:02:50 +0800 | [diff] [blame] | 366 | */ |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 367 | if (is_mx6ull()) { |
| 368 | val = readl(&fuse->mem0); |
| 369 | val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT; |
| 370 | val &= 0x7; |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 371 | |
Peng Fan | 656d233 | 2016-10-08 17:03:00 +0800 | [diff] [blame] | 372 | writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, |
| 373 | &anatop->ana_misc0_set); |
| 374 | } |
| 375 | } |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 376 | |
Fabio Estevam | 3e59fa9 | 2019-11-04 09:44:34 -0300 | [diff] [blame] | 377 | #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) |
| 378 | static void noc_setup(void) |
| 379 | { |
| 380 | enable_ipu_clock(); |
| 381 | |
| 382 | writel(0x80000201, 0xbb0608); |
| 383 | /* Bypass IPU1 QoS generator */ |
| 384 | writel(0x00000002, 0x00bb048c); |
| 385 | /* Bypass IPU2 QoS generator */ |
| 386 | writel(0x00000002, 0x00bb050c); |
| 387 | /* Bandwidth THR for of PRE0 */ |
| 388 | writel(0x00000200, 0x00bb0690); |
| 389 | /* Bandwidth THR for of PRE1 */ |
| 390 | writel(0x00000200, 0x00bb0710); |
| 391 | /* Bandwidth THR for of PRE2 */ |
| 392 | writel(0x00000200, 0x00bb0790); |
| 393 | /* Bandwidth THR for of PRE3 */ |
| 394 | writel(0x00000200, 0x00bb0810); |
| 395 | /* Saturation THR for of PRE0 */ |
| 396 | writel(0x00000010, 0x00bb0694); |
| 397 | /* Saturation THR for of PRE1 */ |
| 398 | writel(0x00000010, 0x00bb0714); |
| 399 | /* Saturation THR for of PRE2 */ |
| 400 | writel(0x00000010, 0x00bb0794); |
| 401 | /* Saturation THR for of PRE */ |
| 402 | writel(0x00000010, 0x00bb0814); |
| 403 | |
| 404 | disable_ipu_clock(); |
| 405 | } |
| 406 | #endif |
| 407 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 408 | int arch_cpu_init(void) |
| 409 | { |
Peng Fan | 946333d | 2017-08-08 16:21:38 +0800 | [diff] [blame] | 410 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 411 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 412 | init_aips(); |
| 413 | |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 414 | /* Need to clear MMDC_CHx_MASK to make warm reset work. */ |
| 415 | clear_mmdc_ch_mask(); |
| 416 | |
Anson Huang | 05a464f | 2014-01-23 14:00:18 +0800 | [diff] [blame] | 417 | /* |
Peng Fan | c0e0ebf | 2015-01-15 14:22:32 +0800 | [diff] [blame] | 418 | * Disable self-bias circuit in the analog bandap. |
| 419 | * The self-bias circuit is used by the bandgap during startup. |
| 420 | * This bit should be set after the bandgap has initialized. |
| 421 | */ |
| 422 | init_bandgap(); |
| 423 | |
Peng Fan | ae86e3f | 2016-08-11 14:02:43 +0800 | [diff] [blame] | 424 | if (!is_mx6ul() && !is_mx6ull()) { |
Peng Fan | f60137e | 2016-03-09 16:44:36 +0800 | [diff] [blame] | 425 | /* |
| 426 | * When low freq boot is enabled, ROM will not set AHB |
| 427 | * freq, so we need to ensure AHB freq is 132MHz in such |
| 428 | * scenario. |
| 429 | * |
| 430 | * To i.MX6UL, when power up, default ARM core and |
| 431 | * AHB rate is 396M and 132M. |
| 432 | */ |
| 433 | if (mxc_get_clock(MXC_ARM_CLK) == 396000000) |
| 434 | set_ahb_rate(132000000); |
| 435 | } |
Anson Huang | 05a464f | 2014-01-23 14:00:18 +0800 | [diff] [blame] | 436 | |
Peng Fan | 2b990ea | 2016-09-28 09:40:27 +0800 | [diff] [blame] | 437 | if (is_mx6ul()) { |
| 438 | if (is_soc_rev(CHIP_REV_1_0) == 0) { |
| 439 | /* |
| 440 | * According to the design team's requirement on |
| 441 | * i.MX6UL,the PMIC_STBY_REQ PAD should be configured |
| 442 | * as open drain 100K (0x0000b8a0). |
| 443 | * Only exists on TO1.0 |
| 444 | */ |
| 445 | writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); |
| 446 | } else { |
| 447 | /* |
| 448 | * From TO1.1, SNVS adds internal pull up control |
| 449 | * for POR_B, the register filed is GPBIT[1:0], |
| 450 | * after system boot up, it can be set to 2b'01 |
| 451 | * to disable internal pull up.It can save about |
| 452 | * 30uA power in SNVS mode. |
| 453 | */ |
| 454 | writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & |
| 455 | (~0x1400)) | 0x400, |
| 456 | MX6UL_SNVS_LP_BASE_ADDR + 0x10); |
| 457 | } |
Peng Fan | a2cba65 | 2016-03-09 16:44:37 +0800 | [diff] [blame] | 458 | } |
| 459 | |
Peng Fan | b64bf0b | 2016-08-11 14:02:46 +0800 | [diff] [blame] | 460 | if (is_mx6ull()) { |
| 461 | /* |
| 462 | * GPBIT[1:0] is suggested to set to 2'b11: |
| 463 | * 2'b00 : always PUP100K |
| 464 | * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL |
| 465 | * 2'b10 : always disable PUP100K |
| 466 | * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL |
| 467 | * register offset is different from i.MX6UL, since |
| 468 | * i.MX6UL is fixed by ECO. |
| 469 | */ |
| 470 | writel(readl(MX6UL_SNVS_LP_BASE_ADDR) | |
| 471 | 0x3, MX6UL_SNVS_LP_BASE_ADDR); |
| 472 | } |
| 473 | |
Peng Fan | a2cba65 | 2016-03-09 16:44:37 +0800 | [diff] [blame] | 474 | /* Set perclk to source from OSC 24MHz */ |
Jorge Ramirez-Ortiz | 76d9539 | 2020-10-23 21:18:41 +0200 | [diff] [blame^] | 475 | if (has_err007805()) |
Peng Fan | fe7052a | 2017-08-08 16:21:39 +0800 | [diff] [blame] | 476 | setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); |
Ye.Li | 622dfbd | 2014-10-30 18:20:58 +0800 | [diff] [blame] | 477 | |
Fabio Estevam | 5f79d46 | 2017-11-23 10:55:33 -0200 | [diff] [blame] | 478 | imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */ |
Stefan Roese | 8338d1d | 2013-04-15 21:14:12 +0000 | [diff] [blame] | 479 | |
Peng Fan | 946333d | 2017-08-08 16:21:38 +0800 | [diff] [blame] | 480 | if (is_mx6sx()) |
| 481 | setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); |
| 482 | |
Dirk Behme | 0adb215 | 2015-03-09 14:48:48 +0100 | [diff] [blame] | 483 | init_src(); |
| 484 | |
Fabio Estevam | 3e59fa9 | 2019-11-04 09:44:34 -0300 | [diff] [blame] | 485 | #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) |
| 486 | if (is_mx6dqp()) |
| 487 | noc_setup(); |
| 488 | #endif |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 489 | return 0; |
| 490 | } |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 491 | |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 492 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 493 | __weak int board_mmc_get_env_dev(int devno) |
| 494 | { |
| 495 | return CONFIG_SYS_MMC_ENV_DEV; |
| 496 | } |
| 497 | |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 498 | static int mmc_get_boot_dev(void) |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 499 | { |
| 500 | struct src *src_regs = (struct src *)SRC_BASE_ADDR; |
| 501 | u32 soc_sbmr = readl(&src_regs->sbmr1); |
| 502 | u32 bootsel; |
| 503 | int devno; |
| 504 | |
| 505 | /* |
| 506 | * Refer to |
| 507 | * "i.MX 6Dual/6Quad Applications Processor Reference Manual" |
| 508 | * Chapter "8.5.3.1 Expansion Device eFUSE Configuration" |
| 509 | * i.MX6SL/SX/UL has same layout. |
| 510 | */ |
| 511 | bootsel = (soc_sbmr & 0x000000FF) >> 6; |
| 512 | |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 513 | /* No boot from sd/mmc */ |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 514 | if (bootsel != 1) |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 515 | return -1; |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 516 | |
| 517 | /* BOOT_CFG2[3] and BOOT_CFG2[4] */ |
| 518 | devno = (soc_sbmr & 0x00001800) >> 11; |
| 519 | |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 520 | return devno; |
| 521 | } |
| 522 | |
| 523 | int mmc_get_env_dev(void) |
| 524 | { |
| 525 | int devno = mmc_get_boot_dev(); |
| 526 | |
| 527 | /* If not boot from sd/mmc, use default value */ |
| 528 | if (devno < 0) |
| 529 | return CONFIG_SYS_MMC_ENV_DEV; |
| 530 | |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 531 | return board_mmc_get_env_dev(devno); |
| 532 | } |
Soeren Moch | bc177f1 | 2016-02-04 14:41:15 +0100 | [diff] [blame] | 533 | |
| 534 | #ifdef CONFIG_SYS_MMC_ENV_PART |
| 535 | __weak int board_mmc_get_env_part(int devno) |
| 536 | { |
| 537 | return CONFIG_SYS_MMC_ENV_PART; |
| 538 | } |
| 539 | |
| 540 | uint mmc_get_env_part(struct mmc *mmc) |
| 541 | { |
| 542 | int devno = mmc_get_boot_dev(); |
| 543 | |
| 544 | /* If not boot from sd/mmc, use default value */ |
| 545 | if (devno < 0) |
| 546 | return CONFIG_SYS_MMC_ENV_PART; |
| 547 | |
| 548 | return board_mmc_get_env_part(devno); |
| 549 | } |
| 550 | #endif |
Peng Fan | 850dbca | 2016-01-28 16:51:26 +0800 | [diff] [blame] | 551 | #endif |
| 552 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 553 | int board_postclk_init(void) |
| 554 | { |
Peng Fan | 81224c4 | 2017-08-08 16:21:35 +0800 | [diff] [blame] | 555 | /* NO LDO SOC on i.MX6SLL */ |
| 556 | if (is_mx6sll()) |
| 557 | return 0; |
| 558 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 559 | set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ |
| 560 | |
| 561 | return 0; |
| 562 | } |
| 563 | |
Anatolij Gustschin | 938734e | 2017-08-28 17:51:33 +0200 | [diff] [blame] | 564 | #ifndef CONFIG_SPL_BUILD |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 565 | /* |
| 566 | * cfg_val will be used for |
| 567 | * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] |
Nikita Kiryanov | 9fba842 | 2014-10-29 19:28:33 +0200 | [diff] [blame] | 568 | * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] |
| 569 | * instead of SBMR1 to determine the boot device. |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 570 | */ |
| 571 | const struct boot_mode soc_boot_modes[] = { |
| 572 | {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, |
| 573 | /* reserved value should start rom usb */ |
Stefan Agner | 6b46c46 | 2017-06-09 13:13:12 -0700 | [diff] [blame] | 574 | #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) |
| 575 | {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, |
| 576 | #else |
Stefan Agner | eb4b62b | 2016-09-15 15:04:39 -0700 | [diff] [blame] | 577 | {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, |
Stefan Agner | 6b46c46 | 2017-06-09 13:13:12 -0700 | [diff] [blame] | 578 | #endif |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 579 | {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, |
Nikolay Dimitrov | 284d901 | 2014-08-10 20:03:07 +0300 | [diff] [blame] | 580 | {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, |
| 581 | {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, |
| 582 | {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, |
| 583 | {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 584 | /* 4 bit bus width */ |
| 585 | {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, |
| 586 | {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| 587 | {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
| 588 | {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
| 589 | {NULL, 0}, |
| 590 | }; |
Anatolij Gustschin | 938734e | 2017-08-28 17:51:33 +0200 | [diff] [blame] | 591 | #endif |
Stephen Warren | 57ab23f | 2013-02-26 12:28:29 +0000 | [diff] [blame] | 592 | |
Peng Fan | 92683e6 | 2015-10-29 15:54:50 +0800 | [diff] [blame] | 593 | void reset_misc(void) |
| 594 | { |
Michael Trimarchi | c41042a | 2018-06-20 23:27:54 +0200 | [diff] [blame] | 595 | #ifndef CONFIG_SPL_BUILD |
Igor Opaniuk | a2ac2aa | 2019-06-19 11:47:08 +0300 | [diff] [blame] | 596 | #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO) |
Peng Fan | 92683e6 | 2015-10-29 15:54:50 +0800 | [diff] [blame] | 597 | lcdif_power_down(); |
| 598 | #endif |
Michael Trimarchi | c41042a | 2018-06-20 23:27:54 +0200 | [diff] [blame] | 599 | #endif |
Peng Fan | 92683e6 | 2015-10-29 15:54:50 +0800 | [diff] [blame] | 600 | } |
| 601 | |
Stephen Warren | 57ab23f | 2013-02-26 12:28:29 +0000 | [diff] [blame] | 602 | void s_init(void) |
| 603 | { |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 604 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 605 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 606 | u32 mask480; |
| 607 | u32 mask528; |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 608 | u32 reg, periph1, periph2; |
Fabio Estevam | 6633e3f | 2014-07-09 16:13:29 -0300 | [diff] [blame] | 609 | |
Peng Fan | 81224c4 | 2017-08-08 16:21:35 +0800 | [diff] [blame] | 610 | if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll()) |
Fabio Estevam | 6633e3f | 2014-07-09 16:13:29 -0300 | [diff] [blame] | 611 | return; |
| 612 | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 613 | /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs |
| 614 | * to make sure PFD is working right, otherwise, PFDs may |
| 615 | * not output clock after reset, MX6DL and MX6SL have added 396M pfd |
| 616 | * workaround in ROM code, as bus clock need it |
| 617 | */ |
| 618 | |
| 619 | mask480 = ANATOP_PFD_CLKGATE_MASK(0) | |
| 620 | ANATOP_PFD_CLKGATE_MASK(1) | |
| 621 | ANATOP_PFD_CLKGATE_MASK(2) | |
| 622 | ANATOP_PFD_CLKGATE_MASK(3); |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 623 | mask528 = ANATOP_PFD_CLKGATE_MASK(1) | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 624 | ANATOP_PFD_CLKGATE_MASK(3); |
| 625 | |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 626 | reg = readl(&ccm->cbcmr); |
| 627 | periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) |
| 628 | >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); |
| 629 | periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) |
| 630 | >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); |
| 631 | |
| 632 | /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ |
| 633 | if ((periph2 != 0x2) && (periph1 != 0x2)) |
| 634 | mask528 |= ANATOP_PFD_CLKGATE_MASK(0); |
| 635 | |
| 636 | if ((periph2 != 0x1) && (periph1 != 0x1) && |
| 637 | (periph2 != 0x3) && (periph1 != 0x3)) |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 638 | mask528 |= ANATOP_PFD_CLKGATE_MASK(2); |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 639 | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 640 | writel(mask480, &anatop->pfd_480_set); |
| 641 | writel(mask528, &anatop->pfd_528_set); |
| 642 | writel(mask480, &anatop->pfd_480_clr); |
| 643 | writel(mask528, &anatop->pfd_528_clr); |
Stephen Warren | 57ab23f | 2013-02-26 12:28:29 +0000 | [diff] [blame] | 644 | } |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 645 | |
| 646 | #ifdef CONFIG_IMX_HDMI |
| 647 | void imx_enable_hdmi_phy(void) |
| 648 | { |
| 649 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
| 650 | u8 reg; |
| 651 | reg = readb(&hdmi->phy_conf0); |
| 652 | reg |= HDMI_PHY_CONF0_PDZ_MASK; |
| 653 | writeb(reg, &hdmi->phy_conf0); |
| 654 | udelay(3000); |
| 655 | reg |= HDMI_PHY_CONF0_ENTMDS_MASK; |
| 656 | writeb(reg, &hdmi->phy_conf0); |
| 657 | udelay(3000); |
| 658 | reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; |
| 659 | writeb(reg, &hdmi->phy_conf0); |
| 660 | writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); |
| 661 | } |
| 662 | |
| 663 | void imx_setup_hdmi(void) |
| 664 | { |
| 665 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 666 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
Peng Fan | 95ae612 | 2016-03-09 16:07:23 +0800 | [diff] [blame] | 667 | int reg, count; |
| 668 | u8 val; |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 669 | |
| 670 | /* Turn on HDMI PHY clock */ |
| 671 | reg = readl(&mxc_ccm->CCGR2); |
| 672 | reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| |
| 673 | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; |
| 674 | writel(reg, &mxc_ccm->CCGR2); |
| 675 | writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); |
| 676 | reg = readl(&mxc_ccm->chsccdr); |
| 677 | reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| |
| 678 | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| |
| 679 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); |
| 680 | reg |= (CHSCCDR_PODF_DIVIDE_BY_3 |
| 681 | << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
| 682 | |(CHSCCDR_IPU_PRE_CLK_540M_PFD |
| 683 | << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); |
| 684 | writel(reg, &mxc_ccm->chsccdr); |
Peng Fan | 95ae612 | 2016-03-09 16:07:23 +0800 | [diff] [blame] | 685 | |
| 686 | /* Clear the overflow condition */ |
| 687 | if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { |
| 688 | /* TMDS software reset */ |
| 689 | writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); |
| 690 | val = readb(&hdmi->fc_invidconf); |
| 691 | /* Need minimum 3 times to write to clear the register */ |
| 692 | for (count = 0 ; count < 5 ; count++) |
| 693 | writeb(val, &hdmi->fc_invidconf); |
| 694 | } |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 695 | } |
| 696 | #endif |
Peng Fan | fb3a3b7 | 2016-01-28 16:55:05 +0800 | [diff] [blame] | 697 | |
Heinrich Schuchardt | cdd0c85 | 2020-06-26 19:57:55 +0200 | [diff] [blame] | 698 | #ifdef CONFIG_ARCH_MISC_INIT |
| 699 | int arch_misc_init(void) |
| 700 | { |
| 701 | #ifdef CONFIG_FSL_CAAM |
| 702 | sec_init(); |
| 703 | #endif |
| 704 | return 0; |
| 705 | } |
| 706 | #endif |
Michael Trimarchi | d9de3f8 | 2018-06-23 16:10:06 +0200 | [diff] [blame] | 707 | |
| 708 | /* |
| 709 | * gpr_init() function is common for boards using MX6S, MX6DL, MX6D, |
| 710 | * MX6Q and MX6QP processors |
| 711 | */ |
Breno Lima | f22b109 | 2017-08-24 10:00:16 -0300 | [diff] [blame] | 712 | void gpr_init(void) |
| 713 | { |
| 714 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 715 | |
Christoph Niedermaier | 2082ebf | 2018-10-19 17:40:54 +0200 | [diff] [blame] | 716 | /* |
| 717 | * If this function is used in a common MX6 spl implementation |
| 718 | * we have to ensure that it is only called for suitable cpu types, |
| 719 | * otherwise it breaks hardware parts like enet1, can1, can2, etc. |
| 720 | */ |
| 721 | if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl()) |
| 722 | return; |
| 723 | |
Breno Lima | f22b109 | 2017-08-24 10:00:16 -0300 | [diff] [blame] | 724 | /* enable AXI cache for VDOA/VPU/IPU */ |
| 725 | writel(0xF00000CF, &iomux->gpr[4]); |
| 726 | if (is_mx6dqp()) { |
| 727 | /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ |
| 728 | writel(0x77177717, &iomux->gpr[6]); |
| 729 | writel(0x77177717, &iomux->gpr[7]); |
| 730 | } else { |
| 731 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
| 732 | writel(0x007F007F, &iomux->gpr[6]); |
| 733 | writel(0x007F007F, &iomux->gpr[7]); |
| 734 | } |
| 735 | } |