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git01.mediatek.com / filogic / uboot / af11600c244b2da474a6cc0d0dd4249b8486bd77 / . / arch / arm / dts / tegra20-colibri.dts
blob: 8eaac4f5a5fd16744c175b18cb1a0fb48363c444 [file] [log] [blame]
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]4
5/ {
6 model = "Toradex Colibri T20";
Marcel Ziswiler2ec89a82015-08-06 00:47:01 +0200[diff] [blame]7 compatible = "toradex,colibri_t20", "nvidia,tegra20";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]13 aliases {
Marcel Ziswiler9a520202015-08-06 00:47:03 +0200[diff] [blame]14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]17 usb0 = "/usb@c5008000";
18 usb1 = "/usb@c5000000";
19 usb2 = "/usb@c5004000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]20 sdhci0 = "/sdhci@c8000600";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]21 };
22
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]23 host1x {
24 status = "okay";
25 dc@54200000 {
26 status = "okay";
27 rgb {
28 status = "okay";
29 nvidia,panel = <&lcd_panel>;
30 };
31 };
32 };
33
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]34 usb@c5000000 {
35 dr_mode = "otg";
36 };
37
38 usb@c5004000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]39 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
40 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]41 };
42
43 usb@c5008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]44 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]45 };
46
47 nand-controller@70008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]48 nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]49 nvidia,width = <8>;
50 nvidia,timing = <15 100 25 80 25 10 15 10 100>;
51
52 nand@0 {
53 reg = <0>;
54 compatible = "nand-flash";
55 };
56 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]57
Marcel Ziswiler9a520202015-08-06 00:47:03 +0200[diff] [blame]58 /*
59 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
60 * board)
61 */
62 i2c@7000c000 {
63 status = "okay";
64 clock-frequency = <100000>;
65 };
66
67 /* GEN2_I2C: unused */
68
69 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
70 i2c@7000c400 {
71 status = "okay";
72 clock-frequency = <100000>;
73 };
74
75 /*
76 * PWR_I2C: power I2C to PMIC and temperature sensor
77 */
78 i2c@7000d000 {
79 status = "okay";
80 clock-frequency = <100000>;
81 };
82
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]83 sdhci@c8000600 {
84 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]85 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]86 bus-width = <4>;
87 };
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]88
89 lcd_panel: panel {
90 clock = <25175000>;
91 xres = <640>;
92 yres = <480>;
93 left-margin = <48>; /* horizontal back porch */
94 right-margin = <16>; /* horizontal front porch */
95 hsync-len = <96>;
96 lower-margin = <11>; /* vertical front porch */
97 upper-margin = <31>; /* vertical back porch */
98 vsync-len = <2>;
99 hsync-active-high;
100 vsync-active-high;
101 nvidia,bits-per-pixel = <16>;
102 nvidia,pwm = <&pwm 0 0>;
103 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
104 nvidia,panel-timings = <0 0 0 0>;
105 };
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]106};