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git01.mediatek.com / filogic / uboot / 757777d91bcc32298cb22c1b44c86d9cb513eb98 / . / cpu / mpc85xx / speed.c
blob: d40cd8c486c9057737117155f64ef6aca27dcb8d [file] [log] [blame]
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]1/*
wdenka445ddf2004-06-09 00:34:46 +0000[diff] [blame]2 * Copyright 2004 Freescale Semiconductor.
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <ppc_asm.tmpl>
30#include <asm/processor.h>
31
32/* --------------------------------------------------------------- */
33
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]34void get_sys_info (sys_info_t * sysInfo)
35{
wdenka445ddf2004-06-09 00:34:46 +0000[diff] [blame]36 DECLARE_GLOBAL_DATA_PTR;
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]37 volatile immap_t *immap = (immap_t *)CFG_IMMR;
38 volatile ccsr_gur_t *gur = &immap->im_gur;
39 uint plat_ratio,e500_ratio;
40
41 plat_ratio = (gur->porpllsr) & 0x0000003e;
42 plat_ratio >>= 1;
43 switch(plat_ratio) {
44 case 0x02:
45 case 0x03:
46 case 0x04:
47 case 0x05:
48 case 0x06:
49 case 0x08:
50 case 0x09:
51 case 0x0a:
52 case 0x0c:
53 case 0x10:
54 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
55 break;
56 default:
57 sysInfo->freqSystemBus = 0;
58 break;
59 }
60
61 e500_ratio = (gur->porpllsr) & 0x003f0000;
62 e500_ratio >>= 16;
63 switch(e500_ratio) {
64 case 0x04:
65 sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
66 break;
67 case 0x05:
68 sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
69 break;
70 case 0x06:
71 sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
72 break;
73 case 0x07:
74 sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
75 break;
76 default:
77 sysInfo->freqProcessor = 0;
78 break;
79 }
80}
81
82int get_clocks (void)
83{
84 DECLARE_GLOBAL_DATA_PTR;
85 sys_info_t sys_info;
86#if defined(CONFIG_MPC8560)
87 volatile immap_t *immap = (immap_t *) CFG_IMMR;
88 uint sccr, dfbrg;
89
90 /* set VCO = 4 * BRG */
91 immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
92 sccr = immap->im_cpm.im_cpm_intctl.sccr;
93 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
94#endif
95 get_sys_info (&sys_info);
96 gd->cpu_clk = sys_info.freqProcessor;
97 gd->bus_clk = sys_info.freqSystemBus;
98#if defined(CONFIG_MPC8560)
99 gd->vco_out = 2*sys_info.freqSystemBus;
100 gd->cpm_clk = gd->vco_out / 2;
101 gd->scc_clk = gd->vco_out / 4;
102 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
103#endif
104
105 if(gd->cpu_clk != 0) return (0);
106 else return (1);
107}
108
109
110/********************************************
111 * get_bus_freq
112 * return system bus freq in Hz
113 *********************************************/
114ulong get_bus_freq (ulong dummy)
115{
116 ulong val;
117
118 sys_info_t sys_info;
119
120 get_sys_info (&sys_info);
121 val = sys_info.freqSystemBus;
122
123 return val;
124}