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git01.mediatek.com / filogic / uboot / 756bf0ef4bab765e29cd3cb70bac8b1aaa014378 / . / arch / arm / dts / k3-am65.dtsi
blob: 4d7b6155a76b7bb3a0d802e19fc8e6692284083a [file] [log] [blame]
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family
4 *
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]11#include <dt-bindings/soc/ti,sci_pm_domain.h>
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]12
Bryan Brattloffd1fe632023-12-29 11:47:01 -0600[diff] [blame]13#include "k3-pinctrl.h"
14
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]15/ {
16 model = "Texas Instruments K3 AM654 SoC";
17 compatible = "ti,am654";
18 interrupt-parent = <&gic500>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 chosen { };
23
24 firmware {
25 optee {
26 compatible = "linaro,optee-tz";
27 method = "smc";
28 };
29
30 psci: psci {
31 compatible = "arm,psci-1.0";
32 method = "smc";
33 };
34 };
35
36 a53_timer0: timer-cl0-cpu0 {
37 compatible = "arm,armv8-timer";
38 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
39 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
40 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
41 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
42 };
43
44 pmu: pmu {
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]45 compatible = "arm,cortex-a53-pmu";
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]46 /* Recommendation from GIC500 TRM Table A.3 */
47 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
48 };
49
Suman Anna3e1addb2020-07-24 17:51:39 -0500[diff] [blame]50 cbass_main: bus@100000 {
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]51 compatible = "simple-bus";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]52 #address-cells = <2>;
53 #size-cells = <2>;
54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
Sekhar Nori956760a2019-08-01 19:13:00 +0530[diff] [blame]60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]61 /* MCUSS Range */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
Suman Anna2604d8d2019-10-17 09:03:08 +0530[diff] [blame]65 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
66 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]67 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]68 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
69 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
70 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]71 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
72 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
Bryan Brattloffd1fe632023-12-29 11:47:01 -0600[diff] [blame]73 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]74 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
75 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
76 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]77
Suman Anna3e1addb2020-07-24 17:51:39 -0500[diff] [blame]78 cbass_mcu: bus@28380000 {
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]79 compatible = "simple-bus";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]80 #address-cells = <2>;
81 #size-cells = <2>;
82 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
83 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
Grygorii Strashkob33dd702019-07-09 10:30:35 +0530[diff] [blame]84 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
Suman Anna2604d8d2019-10-17 09:03:08 +0530[diff] [blame]85 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
86 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]87 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]88 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
89 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
90 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]91 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
92 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
93 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
94 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]95
Suman Anna3e1addb2020-07-24 17:51:39 -0500[diff] [blame]96 cbass_wakeup: bus@42040000 {
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]97 compatible = "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 /* WKUP Basic peripherals */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]101 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]102 };
103 };
104 };
105};
106
107/* Now include the peripherals for each bus segments */
108#include "k3-am65-main.dtsi"
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]109#include "k3-am65-mcu.dtsi"
110#include "k3-am65-wakeup.dtsi"