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git01.mediatek.com / filogic / uboot / 756bf0ef4bab765e29cd3cb70bac8b1aaa014378 / . / arch / arm / dts / imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
blob: cf2a87a9b9037462422dc15a72f16a349effccaf [file] [log] [blame]
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 * Copyright (c) 2020 Amarula Solutons(India)
5 */
6
7#include "imx8mp-u-boot.dtsi"
8
9/ {
10 wdt-reboot {
11 compatible = "wdt-reboot";
12 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]14 };
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]15};
16
17&reg_usdhc2_vmmc {
18 u-boot,off-on-delay-us = <20000>;
19};
20
21&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]23};
24
25&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]27};
28
29&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]31};
32
33&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]35};
36
37&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]39};
40
41&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]43};
44
45&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]47};
48
49&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]51};
52
53&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]55};
56
57&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]59};
60
61&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]63};
64
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]65&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]67};
68
69&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]71};
72
73&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]75};
76
77&i2c4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]79};
80
81&i2c5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]83};
84
85&i2c6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]87};
88
89&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]91};
92
93&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]95 sd-uhs-sdr104;
96 sd-uhs-ddr50;
97 no-1-8-v;
98};
99
100&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]102 mmc-hs400-1_8v;
103 mmc-hs400-enhanced-strobe;
104};
105
106&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]108};
109
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]110&ethphy0 {
111 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
112 reset-delay-us = <15000>;
113 reset-post-delay-us = <100000>;
114};
115
116&fec {
117 phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
118 phy-reset-duration = <15>;
119 phy-reset-post-delay = <100>;
120};