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git01.mediatek.com / filogic / uboot / 7436e8c1d514ccb317cacc20fab3b63f8910babb / . / arch / x86 / include / asm / intel_opregion.h
blob: fb3e38617e4418ed883925a514dfec6c47dbd938 [file] [log] [blame]
Simon Glass057427c2020-09-22 12:45:03 -0600[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Writing IntelGraphicsMem table for ACPI
4 *
5 * Copyright 2019 Google LLC
6 * Modified from coreboot src/soc/intel/gma/opregion.h
7 */
8
9#ifndef _ASM_INTEL_OPREGION_H_
10#define _ASM_INTEL_OPREGION_H_
11
12#define VBT_SIGNATURE 0x54425624
13
14/* IGD PCI Configuration register */
15#define ASLS 0xfc /* OpRegion Base */
16#define SWSCI 0xe8 /* SWSCI Register */
17#define SWSMISCI 0xe0 /* SWSMISCI Register */
18#define GSSCIE BIT(0) /* SCI Event trigger */
19#define SMISCISEL BIT(15) /* Select SMI or SCI event source */
20
21/* mailbox 0: header */
22struct __packed opregion_header {
23 u8 signature[16]; /* Offset 0 OpRegion signature */
24 u32 size; /* Offset 16 OpRegion size */
25 u32 version; /* Offset 20 OpRegion structure version */
26 u8 sbios_version[32]; /* Offset 24 System BIOS build version */
27 u8 vbios_version[16]; /* Offset 56 Video BIOS build version */
28 u8 driver_version[16]; /* Offset 72 Graphic drvr build version */
29 u32 mailboxes; /* Offset 88 Mailboxes supported */
30 u32 dmod; /* Offset 92 Driver Model */
31 u32 pcon; /* Offset 96 Platform Capabilities */
32 u16 dver[16]; /* Offset 100 GOP Version */
33 u8 reserved[124]; /* Offset 132 Reserved */
34};
35
36#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
37#define IGD_OPREGION_VERSION 2
38
39#define IGD_MBOX1 BIT(0)
40#define IGD_MBOX2 BIT(1)
41#define IGD_MBOX3 BIT(2)
42#define IGD_MBOX4 BIT(3)
43#define IGD_MBOX5 BIT(4)
44
45#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
46 IGD_MBOX4 | IGD_MBOX5)
47#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
48
49#define SBIOS_VERSION_SIZE 32
50
51/* mailbox 1: public ACPI methods */
52struct __packed opregion_mailbox1 {
53 u32 drdy; /* Offset 0 Driver readiness */
54 u32 csts; /* Offset 4 Status */
55 u32 cevt; /* Offset 8 Current event */
56 u8 reserved[20]; /* Offset 12 Reserved */
57 u32 didl; /* Offset 32 Supported display device 1 */
58 u32 ddl2; /* Offset 36 Supported display device 2 */
59 u32 ddl3; /* Offset 40 Supported display device 3 */
60 u32 ddl4; /* Offset 44 Supported display device 4 */
61 u32 ddl5; /* Offset 48 Supported display device 5 */
62 u32 ddl6; /* Offset 52 Supported display device 6 */
63 u32 ddl7; /* Offset 56 Supported display device 7 */
64 u32 ddl8; /* Offset 60 Supported display device 8 */
65 u32 cpdl; /* Offset 64 Currently present display device 1 */
66 u32 cpl2; /* Offset 68 Currently present display device 2 */
67 u32 cpl3; /* Offset 72 Currently present display device 3 */
68 u32 cpl4; /* Offset 76 Currently present display device 4 */
69 u32 cpl5; /* Offset 80 Currently present display device 5 */
70 u32 cpl6; /* Offset 84 Currently present display device 6 */
71 u32 cpl7; /* Offset 88 Currently present display device 7 */
72 u32 cpl8; /* Offset 92 Currently present display device 8 */
73 u32 cadl; /* Offset 96 Currently active display device 1 */
74 u32 cal2; /* Offset 100 Currently active display device 2 */
75 u32 cal3; /* Offset 104 Currently active display device 3 */
76 u32 cal4; /* Offset 108 Currently active display device 4 */
77 u32 cal5; /* Offset 112 Currently active display device 5 */
78 u32 cal6; /* Offset 116 Currently active display device 6 */
79 u32 cal7; /* Offset 120 Currently active display device 7 */
80 u32 cal8; /* Offset 124 Currently active display device 8 */
81 u32 nadl; /* Offset 128 Next active device 1 */
82 u32 ndl2; /* Offset 132 Next active device 2 */
83 u32 ndl3; /* Offset 136 Next active device 3 */
84 u32 ndl4; /* Offset 140 Next active device 4 */
85 u32 ndl5; /* Offset 144 Next active device 5 */
86 u32 ndl6; /* Offset 148 Next active device 6 */
87 u32 ndl7; /* Offset 152 Next active device 7 */
88 u32 ndl8; /* Offset 156 Next active device 8 */
89 u32 aslp; /* Offset 160 ASL sleep timeout */
90 u32 tidx; /* Offset 164 Toggle table index */
91 u32 chpd; /* Offset 168 Current hot plug enable indicator */
92 u32 clid; /* Offset 172 Current lid state indicator */
93 u32 cdck; /* Offset 176 Current docking state indicator */
94 u32 sxsw; /* Offset 180 Display Switch notification on Sx State
95 * resume
96 */
97 u32 evts; /* Offset 184 Events supported by ASL */
98 u32 cnot; /* Offset 188 Current OS Notification */
99 u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */
100 u32 ddl9; /* Offset 196 Extended Supported display device 1 */
101 u32 dd10; /* Offset 200 Extended Supported display device 2 */
102 u32 dd11; /* Offset 204 Extended Supported display device 3 */
103 u32 dd12; /* Offset 208 Extended Supported display device 4 */
104 u32 dd13; /* Offset 212 Extended Supported display device 5 */
105 u32 dd14; /* Offset 216 Extended Supported display device 6 */
106 u32 dd15; /* Offset 220 Extended Supported display device 7 */
107 u32 cpl9; /* Offset 224 Extended Currently present device 1 */
108 u32 cp10; /* Offset 228 Extended Currently present device 2 */
109 u32 cp11; /* Offset 232 Extended Currently present device 3 */
110 u32 cp12; /* Offset 236 Extended Currently present device 4 */
111 u32 cp13; /* Offset 240 Extended Currently present device 5 */
112 u32 cp14; /* Offset 244 Extended Currently present device 6 */
113 u32 cp15; /* Offset 248 Extended Currently present device 7 */
114 u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */
115};
116
117/* mailbox 2: software sci interface */
118struct __packed opregion_mailbox2 {
119 u32 scic; /* Offset 0 Software SCI function number parameters */
120 u32 parm; /* Offset 4 Software SCI function number parameters */
121 u32 dslp; /* Offset 8 Driver sleep timeout */
122 u8 reserved[244]; /* Offset 12 Reserved */
123};
124
125/* mailbox 3: power conservation */
126struct __packed opregion_mailbox3 {
127 u32 ardy; /* Offset 0 Driver readiness */
128 u32 aslc; /* Offset 4 ASLE interrupt command / status */
129 u32 tche; /* Offset 8 Technology enabled indicator */
130 u32 alsi; /* Offset 12 Current ALS illuminance reading */
131 u32 bclp; /* Offset 16 Backlight britness to set */
132 u32 pfit; /* Offset 20 Panel fitting Request */
133 u32 cblv; /* Offset 24 Brightness Current State */
134 /* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */
135 u16 bclm[20];
136 u32 cpfm; /* Offset 68 Panel Fitting Current Mode */
137 u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */
138 u8 plut[74]; /* Offset 76 Panel Look Up Table */
139 /* Offset 150 PWM Frequency and Minimum Brightness */
140 u32 pfmb;
141 u32 ccdv; /* Offset 154 Color Correction Default Values */
142 u32 pcft; /* Offset 158 Power Conservation Features */
143 u32 srot; /* Offset 162 Supported Rotation angle */
144 u32 iuer; /* Offset 166 Intel Ultrabook Event Register */
145 u64 fdsp; /* Offset 170 FFS Display Physical address */
146 u32 fdss; /* Offset 178 FFS Display Size */
147 u32 stat; /* Offset 182 State Indicator */
148 /*
149 * Offset 186 (Igd opregion offset 0x3BAh)
150 * Physical address of Raw VBT data
151 */
152 u64 rvda;
153 /* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */
154 u32 rvds;
155 u8 reserved[58]; /* Offset 198 Reserved */
156};
157
158#define IGD_BACKLIGHT_BRIGHTNESS 0xff
159#define IGD_INITIAL_BRIGHTNESS 0x64
160
161#define IGD_FIELD_VALID BIT(31)
162#define IGD_WORD_FIELD_VALID BIT(15)
163#define IGD_PFIT_STRETCH 6
164
165/* mailbox 4: vbt */
166struct __packed opregion_vbt {
167 u8 gvd1[6 << 10];
168};
169
170/* Mailbox 5: BIOS to Driver Notification Extension */
171struct __packed opregion_mailbox5 {
172 u32 phed; /* Offset 7168 Panel Header */
173 u8 bddc[256]; /* Offset 7172 Panel EDID */
174 u8 reserved[764]; /* Offset 7428 764 bytes */
175};
176
177/* IGD OpRegion */
178struct __packed igd_opregion {
179 struct opregion_header header;
180 struct opregion_mailbox1 mailbox1;
181 struct opregion_mailbox2 mailbox2;
182 struct opregion_mailbox3 mailbox3;
183 struct opregion_vbt vbt;
184 struct opregion_mailbox5 mailbox5;
185};
186
187/* Intel Video BIOS (Option ROM) */
188struct __packed optionrom_header {
189 u16 signature;
190 u8 size;
191 u8 reserved[21];
192 u16 pcir_offset;
193 u16 vbt_offset;
194};
195
196#define OPROM_SIGNATURE 0xaa55
197
198struct __packed optionrom_pcir {
199 u32 signature;
200 u16 vendor;
201 u16 device;
202 u16 reserved1;
203 u16 length;
204 u8 revision;
205 u8 classcode[3];
206 u16 imagelength;
207 u16 coderevision;
208 u8 codetype;
209 u8 indicator;
210 u16 reserved2;
211};
212
213struct __packed optionrom_vbt {
214 u8 hdr_signature[20];
215 u16 hdr_version;
216 u16 hdr_size;
217 u16 hdr_vbt_size;
218 u8 hdr_vbt_checksum;
219 u8 hdr_reserved;
220 u32 hdr_vbt_datablock;
221 u32 hdr_aim[4];
222 u8 datahdr_signature[16];
223 u16 datahdr_version;
224 u16 datahdr_size;
225 u16 datahdr_datablocksize;
226 u8 coreblock_id;
227 u16 coreblock_size;
228 u16 coreblock_biossize;
229 u8 coreblock_biostype;
230 u8 coreblock_releasestatus;
231 u8 coreblock_hwsupported;
232 u8 coreblock_integratedhw;
233 u8 coreblock_biosbuild[4];
234 u8 coreblock_biossignon[155];
235};
236
237/**
238 * intel_gma_init_igd_opregion() - Initialise IGD OpRegion
239 *
240 * This is called from ACPI code and OS drivers
241 *
242 * @return 0 if OK, -ve on error
243 */
244int intel_gma_init_igd_opregion(struct udevice *dev,
245 struct igd_opregion *opregion);
246
247#endif /* _ASM_INTEL_OPREGION_H_ */