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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tim Harvey552c3582014-03-06 07:46:30 -08002/*
3 * Copyright (C) 2013 Gateworks Corporation
4 *
5 * Author: Tim Harvey <tharvey@gateworks.com>
Tim Harvey552c3582014-03-06 07:46:30 -08006 */
7
8#include <common.h>
Tim Harvey552c3582014-03-06 07:46:30 -08009#include <asm/arch/clock.h>
Tim Harvey0cee2242015-05-08 18:28:35 -070010#include <asm/arch/crm_regs.h>
Tim Harvey552c3582014-03-06 07:46:30 -080011#include <asm/arch/mx6-pins.h>
Tim Harveyfb64cc72014-04-25 15:39:07 -070012#include <asm/arch/mxc_hdmi.h>
Tim Harvey552c3582014-03-06 07:46:30 -080013#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Tim Harvey552c3582014-03-06 07:46:30 -080015#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020016#include <asm/mach-imx/boot_mode.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020017#include <asm/mach-imx/video.h>
Simon Glassd9a766f2017-05-17 08:23:00 -060018#include <asm/setup.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060019#include <env.h>
Tim Harvey8d2d8df2016-05-24 11:03:55 -070020#include <hwconfig.h>
Tim Harvey0cee2242015-05-08 18:28:35 -070021#include <linux/ctype.h>
Tim Harvey552c3582014-03-06 07:46:30 -080022#include <miiphy.h>
Tim Harvey552c3582014-03-06 07:46:30 -080023#include <mtd_node.h>
Simon Glassdbd79542020-05-10 11:40:11 -060024#include <linux/delay.h>
Tim Harvey552c3582014-03-06 07:46:30 -080025#include <power/pmic.h>
Tim Harvey552c3582014-03-06 07:46:30 -080026#include <fdt_support.h>
27#include <jffs2/load_kernel.h>
Tim Harvey552c3582014-03-06 07:46:30 -080028
29#include "gsc.h"
Tim Harvey0cee2242015-05-08 18:28:35 -070030#include "common.h"
Tim Harvey552c3582014-03-06 07:46:30 -080031
32DECLARE_GLOBAL_DATA_PTR;
33
Tim Harvey26993362014-08-07 22:35:49 -070034
Tim Harvey552c3582014-03-06 07:46:30 -080035/*
36 * EEPROM board info struct populated by read_eeprom so that we only have to
37 * read it once.
38 */
Tim Harvey0da2c522014-08-07 22:35:45 -070039struct ventana_board_info ventana_info;
Tim Harvey8b92bdf2015-04-08 12:54:43 -070040static int board_type;
Tim Harvey552c3582014-03-06 07:46:30 -080041
Tim Harvey552c3582014-03-06 07:46:30 -080042#ifdef CONFIG_USB_EHCI_MX6
Tim Harvey1112b4e2021-03-01 14:33:34 -080043/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
Tim Harvey552c3582014-03-06 07:46:30 -080044int board_ehci_hcd_init(int port)
45{
Tim Harveyf1f41db2015-05-08 18:28:28 -070046 int gpio;
Tim Harvey552c3582014-03-06 07:46:30 -080047
Tim Harvey1112b4e2021-03-01 14:33:34 -080048 /* USB HUB is always on P1 */
49 if (port == 0)
50 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -080051
Tim Harveydb7edfa2015-05-26 11:04:54 -070052 /* Reset USB HUB */
53 switch (board_type) {
54 case GW53xx:
55 case GW552x:
Tim Harveyb7c48a92019-02-04 13:10:54 -080056 case GW5906:
Tim Harveyf1f41db2015-05-08 18:28:28 -070057 gpio = (IMX_GPIO_NR(1, 9));
Tim Harvey552c3582014-03-06 07:46:30 -080058 break;
Tim Harveydb7edfa2015-05-26 11:04:54 -070059 case GW54proto:
60 case GW54xx:
Tim Harveyf1f41db2015-05-08 18:28:28 -070061 gpio = (IMX_GPIO_NR(1, 16));
Tim Harvey552c3582014-03-06 07:46:30 -080062 break;
Tim Harveyf1f41db2015-05-08 18:28:28 -070063 default:
64 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -080065 }
66
Tim Harveyf1f41db2015-05-08 18:28:28 -070067 /* request and toggle hub rst */
68 gpio_request(gpio, "usb_hub_rst#");
69 gpio_direction_output(gpio, 0);
70 mdelay(2);
71 gpio_set_value(gpio, 1);
72
Tim Harvey552c3582014-03-06 07:46:30 -080073 return 0;
74}
Tim Harvey552c3582014-03-06 07:46:30 -080075#endif /* CONFIG_USB_EHCI_MX6 */
76
Tim Harvey552c3582014-03-06 07:46:30 -080077/* configure eth0 PHY board-specific LED behavior */
78int board_phy_config(struct phy_device *phydev)
79{
80 unsigned short val;
81
82 /* Marvel 88E1510 */
83 if (phydev->phy_id == 0x1410dd1) {
Tim Harveyb25b7582021-06-11 12:46:26 -070084 puts("MV88E1510");
Tim Harvey552c3582014-03-06 07:46:30 -080085 /*
86 * Page 3, Register 16: LED[2:0] Function Control Register
87 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
88 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
89 */
90 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
91 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
92 val &= 0xff00;
93 val |= 0x0017;
94 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
95 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
96 }
97
Tim Harvey4533c902017-03-17 07:32:21 -070098 /* TI DP83867 */
99 else if (phydev->phy_id == 0x2000a231) {
Tim Harveyb25b7582021-06-11 12:46:26 -0700100 puts("TIDP83867 ");
Tim Harvey1662ad32021-06-11 12:46:25 -0700101 /* LED configuration */
102 val = 0;
103 val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
104 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
105 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
106
Tim Harvey4533c902017-03-17 07:32:21 -0700107 /* configure register 0x170 for ref CLKOUT */
108 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
109 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
110 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
111 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
112 val &= ~0x1f00;
113 val |= 0x0b00; /* chD tx clock*/
114 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
115 }
116
Tim Harvey552c3582014-03-06 07:46:30 -0800117 if (phydev->drv->config)
118 phydev->drv->config(phydev);
119
120 return 0;
121}
Tim Harvey63537792017-03-17 07:30:38 -0700122
123#ifdef CONFIG_MV88E61XX_SWITCH
124int mv88e61xx_hw_reset(struct phy_device *phydev)
125{
126 struct mii_dev *bus = phydev->bus;
127
128 /* GPIO[0] output, CLK125 */
129 debug("enabling RGMII_REFCLK\n");
130 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
131 0x1a /*MV_SCRATCH_MISC*/,
132 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
133 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
134 0x1a /*MV_SCRATCH_MISC*/,
135 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
136
137 /* RGMII delay - Physical Control register bit[15:14] */
138 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
139 /* forced 1000mbps full-duplex link */
140 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
141 phydev->autoneg = AUTONEG_DISABLE;
142 phydev->speed = SPEED_1000;
143 phydev->duplex = DUPLEX_FULL;
144
Tim Harvey8c9d3932019-02-04 13:10:47 -0800145 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
146 bus->write(bus, 0x10, 0, 0x16, 0x8088);
147 bus->write(bus, 0x11, 0, 0x16, 0x8088);
148 bus->write(bus, 0x12, 0, 0x16, 0x8088);
149 bus->write(bus, 0x13, 0, 0x16, 0x8088);
Tim Harvey63537792017-03-17 07:30:38 -0700150
151 return 0;
152}
153#endif // CONFIG_MV88E61XX_SWITCH
Tim Harvey552c3582014-03-06 07:46:30 -0800154
Tim Harveyfb64cc72014-04-25 15:39:07 -0700155#if defined(CONFIG_VIDEO_IPUV3)
Tim Harveyfb64cc72014-04-25 15:39:07 -0700156static void enable_hdmi(struct display_info_t const *dev)
157{
158 imx_enable_hdmi_phy();
159}
160
161static int detect_i2c(struct display_info_t const *dev)
162{
163 return i2c_set_bus_num(dev->bus) == 0 &&
164 i2c_probe(dev->addr) == 0;
165}
166
167static void enable_lvds(struct display_info_t const *dev)
168{
169 struct iomuxc *iomux = (struct iomuxc *)
170 IOMUXC_BASE_ADDR;
171
172 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
173 u32 reg = readl(&iomux->gpr[2]);
174 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
175 writel(reg, &iomux->gpr[2]);
176
177 /* Enable Backlight */
Tim Harveya67e07f2016-05-24 11:03:53 -0700178 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
179 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
Tim Harveyf1f41db2015-05-08 18:28:28 -0700180 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
Tim Harvey26993362014-08-07 22:35:49 -0700181 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
Tim Harveyfb64cc72014-04-25 15:39:07 -0700182 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
183}
184
185struct display_info_t const displays[] = {{
186 /* HDMI Output */
187 .bus = -1,
188 .addr = 0,
189 .pixfmt = IPU_PIX_FMT_RGB24,
190 .detect = detect_hdmi,
191 .enable = enable_hdmi,
192 .mode = {
193 .name = "HDMI",
194 .refresh = 60,
195 .xres = 1024,
196 .yres = 768,
197 .pixclock = 15385,
198 .left_margin = 220,
199 .right_margin = 40,
200 .upper_margin = 21,
201 .lower_margin = 7,
202 .hsync_len = 60,
203 .vsync_len = 10,
204 .sync = FB_SYNC_EXT,
205 .vmode = FB_VMODE_NONINTERLACED
206} }, {
207 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
208 .bus = 2,
209 .addr = 0x4,
210 .pixfmt = IPU_PIX_FMT_LVDS666,
211 .detect = detect_i2c,
212 .enable = enable_lvds,
213 .mode = {
214 .name = "Hannstar-XGA",
215 .refresh = 60,
216 .xres = 1024,
217 .yres = 768,
218 .pixclock = 15385,
219 .left_margin = 220,
220 .right_margin = 40,
221 .upper_margin = 21,
222 .lower_margin = 7,
223 .hsync_len = 60,
224 .vsync_len = 10,
225 .sync = FB_SYNC_EXT,
226 .vmode = FB_VMODE_NONINTERLACED
Tim Harveya20bd632015-04-08 12:54:57 -0700227} }, {
228 /* DLC700JMG-T-4 */
Tim Harveybe786e72019-02-04 13:10:53 -0800229 .bus = 2,
230 .addr = 0x38,
Tim Harveya20bd632015-04-08 12:54:57 -0700231 .detect = NULL,
232 .enable = enable_lvds,
233 .pixfmt = IPU_PIX_FMT_LVDS666,
234 .mode = {
235 .name = "DLC700JMGT4",
236 .refresh = 60,
237 .xres = 1024, /* 1024x600active pixels */
238 .yres = 600,
239 .pixclock = 15385, /* 64MHz */
240 .left_margin = 220,
241 .right_margin = 40,
242 .upper_margin = 21,
243 .lower_margin = 7,
244 .hsync_len = 60,
245 .vsync_len = 10,
246 .sync = FB_SYNC_EXT,
247 .vmode = FB_VMODE_NONINTERLACED
248} }, {
Tim Harvey87a86452021-06-11 12:46:27 -0700249 /* DLC0700XDP21LF-C-1 */
250 .bus = 0,
251 .addr = 0,
252 .detect = NULL,
253 .enable = enable_lvds,
254 .pixfmt = IPU_PIX_FMT_LVDS666,
255 .mode = {
256 .name = "DLC0700XDP21LF",
257 .refresh = 60,
258 .xres = 1024, /* 1024x600active pixels */
259 .yres = 600,
260 .pixclock = 15385, /* 64MHz */
261 .left_margin = 220,
262 .right_margin = 40,
263 .upper_margin = 21,
264 .lower_margin = 7,
265 .hsync_len = 60,
266 .vsync_len = 10,
267 .sync = FB_SYNC_EXT,
268 .vmode = FB_VMODE_NONINTERLACED
269} }, {
Tim Harveya20bd632015-04-08 12:54:57 -0700270 /* DLC800FIG-T-3 */
Tim Harveybe786e72019-02-04 13:10:53 -0800271 .bus = 2,
272 .addr = 0x14,
Tim Harveya20bd632015-04-08 12:54:57 -0700273 .detect = NULL,
274 .enable = enable_lvds,
275 .pixfmt = IPU_PIX_FMT_LVDS666,
276 .mode = {
277 .name = "DLC800FIGT3",
278 .refresh = 60,
279 .xres = 1024, /* 1024x768 active pixels */
280 .yres = 768,
281 .pixclock = 15385, /* 64MHz */
282 .left_margin = 220,
283 .right_margin = 40,
284 .upper_margin = 21,
285 .lower_margin = 7,
286 .hsync_len = 60,
287 .vsync_len = 10,
288 .sync = FB_SYNC_EXT,
289 .vmode = FB_VMODE_NONINTERLACED
Tim Harveyc34e59e2019-02-04 13:10:51 -0800290} }, {
291 .bus = 2,
292 .addr = 0x5d,
293 .detect = detect_i2c,
294 .enable = enable_lvds,
295 .pixfmt = IPU_PIX_FMT_LVDS666,
296 .mode = {
297 .name = "Z101WX01",
298 .refresh = 60,
299 .xres = 1280,
300 .yres = 800,
301 .pixclock = 15385, /* 64MHz */
302 .left_margin = 220,
303 .right_margin = 40,
304 .upper_margin = 21,
305 .lower_margin = 7,
306 .hsync_len = 60,
307 .vsync_len = 10,
308 .sync = FB_SYNC_EXT,
309 .vmode = FB_VMODE_NONINTERLACED
310 }
311},
312};
Tim Harveyfb64cc72014-04-25 15:39:07 -0700313size_t display_count = ARRAY_SIZE(displays);
314
315static void setup_display(void)
316{
317 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
318 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
319 int reg;
320
321 enable_ipu_clock();
322 imx_setup_hdmi();
323 /* Turn on LDB0,IPU,IPU DI0 clocks */
324 reg = __raw_readl(&mxc_ccm->CCGR3);
325 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
326 writel(reg, &mxc_ccm->CCGR3);
327
328 /* set LDB0, LDB1 clk select to 011/011 */
329 reg = readl(&mxc_ccm->cs2cdr);
330 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
331 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
332 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
333 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
334 writel(reg, &mxc_ccm->cs2cdr);
335
336 reg = readl(&mxc_ccm->cscmr2);
337 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
338 writel(reg, &mxc_ccm->cscmr2);
339
340 reg = readl(&mxc_ccm->chsccdr);
341 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
342 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
343 writel(reg, &mxc_ccm->chsccdr);
344
345 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
346 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
347 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
348 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
349 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
350 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
351 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
352 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
353 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
354 writel(reg, &iomux->gpr[2]);
355
356 reg = readl(&iomux->gpr[3]);
357 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
358 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
359 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
360 writel(reg, &iomux->gpr[3]);
361
Tim Harveya67e07f2016-05-24 11:03:53 -0700362 /* LVDS Backlight GPIO on LVDS connector - output low */
Tim Harvey26993362014-08-07 22:35:49 -0700363 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
Tim Harveyfb64cc72014-04-25 15:39:07 -0700364 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
365}
366#endif /* CONFIG_VIDEO_IPUV3 */
367
Tim Harvey0dff16f2014-05-05 08:22:25 -0700368/* setup board specific PMIC */
369int power_init_board(void)
370{
Tim Harvey195bc972015-05-08 18:28:37 -0700371 setup_pmic();
Tim Harvey0dff16f2014-05-05 08:22:25 -0700372 return 0;
373}
374
Tim Harvey7367b392021-07-06 10:19:09 -0700375int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
Tim Harvey552c3582014-03-06 07:46:30 -0800376{
377 if (board_type < GW_UNKNOWN) {
Tim Harvey02fb5922014-06-02 16:13:26 -0700378 uint pin = gpio_cfg[board_type].pcie_rst;
Tim Harveyf1f41db2015-05-08 18:28:28 -0700379 gpio_request(pin, "pci_rst#");
Tim Harvey02fb5922014-06-02 16:13:26 -0700380 gpio_direction_output(pin, 0);
Tim Harvey552c3582014-03-06 07:46:30 -0800381 mdelay(50);
Tim Harvey02fb5922014-06-02 16:13:26 -0700382 gpio_direction_output(pin, 1);
Tim Harvey552c3582014-03-06 07:46:30 -0800383 }
384 return 0;
385}
Tim Harvey33791d52014-08-07 22:49:57 -0700386
387/*
388 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
389 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
390 * properly and assert reset for 100ms.
391 */
Tim Harveybfb240a2016-06-17 06:10:41 -0700392#define MAX_PCI_DEVS 32
393struct pci_dev {
394 pci_dev_t devfn;
Tim Harvey6ce10d52021-05-03 11:21:27 -0700395 struct udevice *dev;
Tim Harveybfb240a2016-06-17 06:10:41 -0700396 unsigned short vendor;
397 unsigned short device;
398 unsigned short class;
399 unsigned short busno; /* subbordinate busno */
400 struct pci_dev *ppar;
401};
402struct pci_dev pci_devs[MAX_PCI_DEVS];
403int pci_devno;
404int pci_bridgeno;
405
Tim Harvey6ce10d52021-05-03 11:21:27 -0700406void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
Tim Harvey33791d52014-08-07 22:49:57 -0700407{
Tim Harvey6ce10d52021-05-03 11:21:27 -0700408 struct pci_child_plat *pdata = dev_get_parent_plat(udev);
Tim Harveybfb240a2016-06-17 06:10:41 -0700409 struct pci_dev *pdev = &pci_devs[pci_devno++];
Tim Harvey6ce10d52021-05-03 11:21:27 -0700410 unsigned short vendor = pdata->vendor;
411 unsigned short device = pdata->device;
412 unsigned int class = pdata->class;
413 pci_dev_t dev = dm_pci_get_bdf(udev);
414 int i;
Tim Harvey33791d52014-08-07 22:49:57 -0700415
416 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
417 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
Tim Harveybfb240a2016-06-17 06:10:41 -0700418
419 /* store array of devs for later use in device-tree fixup */
Tim Harvey6ce10d52021-05-03 11:21:27 -0700420 pdev->dev = udev;
Tim Harveybfb240a2016-06-17 06:10:41 -0700421 pdev->devfn = dev;
422 pdev->vendor = vendor;
423 pdev->device = device;
424 pdev->class = class;
425 pdev->ppar = NULL;
426 if (class == PCI_CLASS_BRIDGE_PCI)
427 pdev->busno = ++pci_bridgeno;
428 else
429 pdev->busno = 0;
430
431 /* fixup RC - it should be 00:00.0 not 00:01.0 */
432 if (PCI_BUS(dev) == 0)
433 pdev->devfn = 0;
434
435 /* find dev's parent */
436 for (i = 0; i < pci_devno; i++) {
437 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
438 pdev->ppar = &pci_devs[i];
439 break;
440 }
441 }
442
443 /* assert downstream PERST# */
Tim Harvey33791d52014-08-07 22:49:57 -0700444 if (vendor == PCI_VENDOR_ID_PLX &&
445 (device & 0xfff0) == 0x8600 &&
446 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
Tim Harvey6ce10d52021-05-03 11:21:27 -0700447 ulong val;
Tim Harvey33791d52014-08-07 22:49:57 -0700448 debug("configuring PLX 860X downstream PERST#\n");
Tim Harvey6ce10d52021-05-03 11:21:27 -0700449 pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
450 val |= 0xaaa8; /* GPIO1-7 outputs */
451 pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
Tim Harvey33791d52014-08-07 22:49:57 -0700452
Tim Harvey6ce10d52021-05-03 11:21:27 -0700453 pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
454 val |= 0xfe; /* GPIO1-7 output high */
455 pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
Tim Harvey33791d52014-08-07 22:49:57 -0700456
457 mdelay(100);
458 }
459}
Tim Harvey552c3582014-03-06 07:46:30 -0800460
461#ifdef CONFIG_SERIAL_TAG
462/*
463 * called when setting up ATAGS before booting kernel
464 * populate serialnum from the following (in order of priority):
465 * serial# env var
466 * eeprom
467 */
468void get_board_serial(struct tag_serialnr *serialnr)
469{
Simon Glass64b723f2017-08-03 12:22:12 -0600470 char *serial = env_get("serial#");
Tim Harvey552c3582014-03-06 07:46:30 -0800471
472 if (serial) {
473 serialnr->high = 0;
474 serialnr->low = simple_strtoul(serial, NULL, 10);
475 } else if (ventana_info.model[0]) {
476 serialnr->high = 0;
477 serialnr->low = ventana_info.serial;
478 } else {
479 serialnr->high = 0;
480 serialnr->low = 0;
481 }
482}
483#endif
484
485/*
486 * Board Support
487 */
488
489int board_early_init_f(void)
490{
Tim Harveyfb64cc72014-04-25 15:39:07 -0700491#if defined(CONFIG_VIDEO_IPUV3)
492 setup_display();
493#endif
Tim Harvey552c3582014-03-06 07:46:30 -0800494 return 0;
495}
496
497int dram_init(void)
498{
Tim Harveybfa2dae2014-06-02 16:13:27 -0700499 gd->ram_size = imx_ddr_size();
Tim Harvey552c3582014-03-06 07:46:30 -0800500 return 0;
501}
502
503int board_init(void)
504{
Fabio Estevamceb74c42014-07-09 17:59:54 -0300505 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
Tim Harvey552c3582014-03-06 07:46:30 -0800506
507 clrsetbits_le32(&iomuxc_regs->gpr[1],
508 IOMUXC_GPR1_OTG_ID_MASK,
509 IOMUXC_GPR1_OTG_ID_GPIO1);
510
511 /* address of linux boot parameters */
512 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
513
Tim Harveyba9f2342019-02-04 13:10:52 -0800514 /* read Gateworks EEPROM into global struct (used later) */
515 setup_ventana_i2c(0);
516 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
517
Tim Harveyd04dc812019-02-04 13:10:49 -0800518 setup_ventana_i2c(1);
519 setup_ventana_i2c(2);
Tim Harvey552c3582014-03-06 07:46:30 -0800520
Tim Harvey0cee2242015-05-08 18:28:35 -0700521 setup_iomux_gpio(board_type, &ventana_info);
Tim Harvey552c3582014-03-06 07:46:30 -0800522
523 return 0;
524}
525
Tim Harvey948202c2021-03-01 14:33:32 -0800526int board_fit_config_name_match(const char *name)
527{
528 static char init;
529 const char *dtb;
530 char buf[32];
531 int i = 0;
532
533 do {
534 dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
535 if (dtb && !strcmp(dtb, name)) {
536 if (!init++)
537 printf("DTB: %s\n", name);
538 return 0;
539 }
540 } while (dtb);
541
542 return -1;
543}
544
Tim Harvey552c3582014-03-06 07:46:30 -0800545#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
546/*
547 * called during late init (after relocation and after board_init())
548 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
549 * EEPROM read.
550 */
551int checkboard(void)
552{
553 struct ventana_board_info *info = &ventana_info;
554 unsigned char buf[4];
555 const char *p;
556 int quiet; /* Quiet or minimal output mode */
557
558 quiet = 0;
Simon Glass64b723f2017-08-03 12:22:12 -0600559 p = env_get("quiet");
Tim Harvey552c3582014-03-06 07:46:30 -0800560 if (p)
561 quiet = simple_strtol(p, NULL, 10);
562 else
Simon Glass6a38e412017-08-03 12:22:09 -0600563 env_set("quiet", "0");
Tim Harvey552c3582014-03-06 07:46:30 -0800564
565 puts("\nGateworks Corporation Copyright 2014\n");
566 if (info->model[0]) {
567 printf("Model: %s\n", info->model);
568 printf("MFGDate: %02x-%02x-%02x%02x\n",
569 info->mfgdate[0], info->mfgdate[1],
570 info->mfgdate[2], info->mfgdate[3]);
571 printf("Serial:%d\n", info->serial);
572 } else {
573 puts("Invalid EEPROM - board will not function fully\n");
574 }
575 if (quiet)
576 return 0;
577
578 /* Display GSC firmware revision/CRC/status */
Tim Harvey92e3d842015-04-08 12:54:59 -0700579 gsc_info(0);
580
Tim Harvey552c3582014-03-06 07:46:30 -0800581 /* Display RTC */
582 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
583 printf("RTC: %d\n",
584 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
585 }
586
587 return 0;
588}
589#endif
590
591#ifdef CONFIG_CMD_BMODE
592/*
593 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
594 * see Table 8-11 and Table 5-9
595 * BOOT_CFG1[7] = 1 (boot from NAND)
596 * BOOT_CFG1[5] = 0 - raw NAND
597 * BOOT_CFG1[4] = 0 - default pad settings
598 * BOOT_CFG1[3:2] = 00 - devices = 1
599 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
600 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
601 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
602 * BOOT_CFG2[0] = 0 - Reset time 12ms
603 */
604static const struct boot_mode board_boot_modes[] = {
605 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
606 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
Tim Harvey659441b2017-03-17 07:31:02 -0700607 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
Tim Harveya2d24c92019-02-04 13:10:50 -0800608 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
Tim Harvey552c3582014-03-06 07:46:30 -0800609 { NULL, 0 },
610};
611#endif
612
613/* late init */
614int misc_init_r(void)
615{
616 struct ventana_board_info *info = &ventana_info;
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700617 char buf[256];
618 int i;
Tim Harvey552c3582014-03-06 07:46:30 -0800619
620 /* set env vars based on EEPROM data */
621 if (ventana_info.model[0]) {
622 char str[16], fdt[36];
623 char *p;
624 const char *cputype = "";
Tim Harvey552c3582014-03-06 07:46:30 -0800625
626 /*
627 * FDT name will be prefixed with CPU type. Three versions
628 * will be created each increasingly generic and bootloader
629 * env scripts will try loading each from most specific to
630 * least.
631 */
Tim Harveybfa2dae2014-06-02 16:13:27 -0700632 if (is_cpu_type(MXC_CPU_MX6Q) ||
633 is_cpu_type(MXC_CPU_MX6D))
Tim Harvey552c3582014-03-06 07:46:30 -0800634 cputype = "imx6q";
Tim Harveybfa2dae2014-06-02 16:13:27 -0700635 else if (is_cpu_type(MXC_CPU_MX6DL) ||
636 is_cpu_type(MXC_CPU_MX6SOLO))
Tim Harvey552c3582014-03-06 07:46:30 -0800637 cputype = "imx6dl";
Simon Glass6a38e412017-08-03 12:22:09 -0600638 env_set("soctype", cputype);
Tim Harvey06d87432014-08-07 22:35:41 -0700639 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
Simon Glass6a38e412017-08-03 12:22:09 -0600640 env_set("flash_layout", "large");
Tim Harvey06d87432014-08-07 22:35:41 -0700641 else
Simon Glass6a38e412017-08-03 12:22:09 -0600642 env_set("flash_layout", "normal");
Tim Harvey552c3582014-03-06 07:46:30 -0800643 memset(str, 0, sizeof(str));
644 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
645 str[i] = tolower(info->model[i]);
Simon Glass6a38e412017-08-03 12:22:09 -0600646 env_set("model", str);
Simon Glass64b723f2017-08-03 12:22:12 -0600647 if (!env_get("fdt_file")) {
Tim Harvey552c3582014-03-06 07:46:30 -0800648 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600649 env_set("fdt_file", fdt);
Tim Harvey552c3582014-03-06 07:46:30 -0800650 }
651 p = strchr(str, '-');
652 if (p) {
653 *p++ = 0;
654
Simon Glass6a38e412017-08-03 12:22:09 -0600655 env_set("model_base", str);
Tim Harveyf6db79a2015-05-26 11:04:56 -0700656 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600657 env_set("fdt_file1", fdt);
Tim Harvey892068c2016-05-24 11:03:58 -0700658 if (board_type != GW551x &&
659 board_type != GW552x &&
Tim Harvey659441b2017-03-17 07:31:02 -0700660 board_type != GW553x &&
661 board_type != GW560x)
Tim Harvey50581832014-08-20 23:35:14 -0700662 str[4] = 'x';
Tim Harvey552c3582014-03-06 07:46:30 -0800663 str[5] = 'x';
664 str[6] = 0;
Tim Harveyf6db79a2015-05-26 11:04:56 -0700665 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600666 env_set("fdt_file2", fdt);
Tim Harvey552c3582014-03-06 07:46:30 -0800667 }
668
669 /* initialize env from EEPROM */
670 if (test_bit(EECONFIG_ETH0, info->config) &&
Simon Glass64b723f2017-08-03 12:22:12 -0600671 !env_get("ethaddr")) {
Simon Glass8551d552017-08-03 12:22:11 -0600672 eth_env_set_enetaddr("ethaddr", info->mac0);
Tim Harvey552c3582014-03-06 07:46:30 -0800673 }
674 if (test_bit(EECONFIG_ETH1, info->config) &&
Simon Glass64b723f2017-08-03 12:22:12 -0600675 !env_get("eth1addr")) {
Simon Glass8551d552017-08-03 12:22:11 -0600676 eth_env_set_enetaddr("eth1addr", info->mac1);
Tim Harvey552c3582014-03-06 07:46:30 -0800677 }
678
679 /* board serial-number */
680 sprintf(str, "%6d", info->serial);
Simon Glass6a38e412017-08-03 12:22:09 -0600681 env_set("serial#", str);
Tim Harvey27770822015-04-08 12:54:51 -0700682
683 /* memory MB */
684 sprintf(str, "%d", (int) (gd->ram_size >> 20));
Simon Glass6a38e412017-08-03 12:22:09 -0600685 env_set("mem_mb", str);
Tim Harvey552c3582014-03-06 07:46:30 -0800686 }
687
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700688 /* Set a non-initialized hwconfig based on board configuration */
Simon Glass64b723f2017-08-03 12:22:12 -0600689 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
Tim Harveyfd6f2392017-03-13 08:51:06 -0700690 buf[0] = 0;
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700691 if (gpio_cfg[board_type].rs232_en)
692 strcat(buf, "rs232;");
693 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
694 char buf1[32];
695 sprintf(buf1, "dio%d:mode=gpio;", i);
696 if (strlen(buf) + strlen(buf1) < sizeof(buf))
697 strcat(buf, buf1);
698 }
Simon Glass6a38e412017-08-03 12:22:09 -0600699 env_set("hwconfig", buf);
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700700 }
Tim Harvey552c3582014-03-06 07:46:30 -0800701
Tim Harvey0cee2242015-05-08 18:28:35 -0700702 /* setup baseboard specific GPIO based on board and env */
703 setup_board_gpio(board_type, info);
Tim Harvey552c3582014-03-06 07:46:30 -0800704
705#ifdef CONFIG_CMD_BMODE
706 add_board_boot_modes(board_boot_modes);
707#endif
708
Tim Harvey40feabb2015-05-08 18:28:36 -0700709 /* disable boot watchdog */
710 gsc_boot_wd_disable();
Tim Harvey552c3582014-03-06 07:46:30 -0800711
712 return 0;
713}
714
Robert P. J. Day3c757002016-05-19 15:23:12 -0400715#ifdef CONFIG_OF_BOARD_SETUP
Tim Harvey552c3582014-03-06 07:46:30 -0800716
Tim Harveycf20e552015-04-08 12:55:01 -0700717static int ft_sethdmiinfmt(void *blob, char *mode)
718{
719 int off;
720
721 if (!mode)
722 return -EINVAL;
723
724 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
725 if (off < 0)
726 return off;
727
728 if (0 == strcasecmp(mode, "yuv422bt656")) {
729 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
730 0x00, 0x00, 0x00 };
731 mode = "422_ccir";
732 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
733 fdt_setprop_u32(blob, off, "vidout_trc", 1);
734 fdt_setprop_u32(blob, off, "vidout_blc", 1);
735 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
736 printf(" set HDMI input mode to %s\n", mode);
737 } else if (0 == strcasecmp(mode, "yuv422smp")) {
738 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
739 0x82, 0x81, 0x00 };
740 mode = "422_smp";
741 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
742 fdt_setprop_u32(blob, off, "vidout_trc", 0);
743 fdt_setprop_u32(blob, off, "vidout_blc", 0);
744 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
745 printf(" set HDMI input mode to %s\n", mode);
746 } else {
747 return -EINVAL;
748 }
749
750 return 0;
751}
752
Tim Harveybfb240a2016-06-17 06:10:41 -0700753#if defined(CONFIG_CMD_PCI)
754#define PCI_ID(x) ( \
755 (PCI_BUS(x->devfn)<<16)| \
756 (PCI_DEV(x->devfn)<<11)| \
757 (PCI_FUNC(x->devfn)<<8) \
758 )
Tim Harveybfb240a2016-06-17 06:10:41 -0700759int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
760{
761 uint32_t reg[5];
762 char node[32];
763 int np;
764
765 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
766 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
767
768 np = fdt_subnode_offset(blob, par, node);
769 if (np >= 0)
770 return np;
771 np = fdt_add_subnode(blob, par, node);
772 if (np < 0) {
773 printf(" %s failed: no space\n", __func__);
774 return np;
775 }
776
777 memset(reg, 0, sizeof(reg));
778 reg[0] = cpu_to_fdt32(PCI_ID(dev));
779 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
780
781 return np;
782}
783
784/* build a path of nested PCI devs for all bridges passed through */
785int fdt_add_pci_path(void *blob, struct pci_dev *dev)
786{
787 struct pci_dev *bridges[MAX_PCI_DEVS];
788 int k, np;
789
790 /* build list of parents */
Tim Harvey984aa0d2019-02-04 13:11:00 -0800791 np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
Tim Harveybfb240a2016-06-17 06:10:41 -0700792 if (np < 0)
793 return np;
794
795 k = 0;
796 while (dev) {
797 bridges[k++] = dev;
798 dev = dev->ppar;
799 };
800
801 /* now add them the to DT in reverse order */
802 while (k--) {
803 np = fdt_add_pci_node(blob, np, bridges[k]);
804 if (np < 0)
805 break;
806 }
807
808 return np;
809}
810
811/*
812 * The GW16082 has a hardware errata errata such that it's
813 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
814 * of this normal PCI interrupt swizzling will not work so we will
815 * provide an irq-map via device-tree.
816 */
817int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
818{
819 int len;
820 int host;
821 uint32_t imap_new[8*4*4];
822 const uint32_t *imap;
823 uint32_t irq[4];
824 uint32_t reg[4];
825 int i;
826
827 /* build irq-map based on host controllers map */
Tim Harvey984aa0d2019-02-04 13:11:00 -0800828 host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
Tim Harveybfb240a2016-06-17 06:10:41 -0700829 if (host < 0) {
830 printf(" %s failed: missing host\n", __func__);
831 return host;
832 }
833
834 /* use interrupt data from root complex's node */
835 imap = fdt_getprop(blob, host, "interrupt-map", &len);
836 if (!imap || len != 128) {
837 printf(" %s failed: invalid interrupt-map\n",
838 __func__);
839 return -FDT_ERR_NOTFOUND;
840 }
841
842 /* obtain irq's of host controller in pin order */
843 for (i = 0; i < 4; i++)
844 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
845
846 /*
847 * determine number of swizzles necessary:
848 * For each bridge we pass through we need to swizzle
849 * the number of the slot we are on.
850 */
851 struct pci_dev *d;
852 int b;
853 b = 0;
854 d = dev->ppar;
855 while(d && d->ppar) {
856 b += PCI_DEV(d->devfn);
857 d = d->ppar;
858 }
859
860 /* create new irq mappings for slots12-15
861 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
862 * J3 AD28 12 INTD INTA
863 * J4 AD29 13 INTC INTD
864 * J5 AD30 14 INTB INTC
865 * J2 AD31 15 INTA INTB
866 */
867 for (i = 0; i < 4; i++) {
868 /* addr matches bus:dev:func */
869 u32 addr = dev->busno << 16 | (12+i) << 11;
870
871 /* default cells from root complex */
872 memcpy(&imap_new[i*32], imap, 128);
873 /* first cell is PCI device address (BDF) */
874 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
875 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
876 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
877 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
878 /* third cell is pin */
879 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
880 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
881 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
882 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
883 /* sixth cell is relative interrupt */
884 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
885 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
886 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
887 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
888 }
889 fdt_setprop(blob, np, "interrupt-map", imap_new,
890 sizeof(imap_new));
891 reg[0] = cpu_to_fdt32(0xfff00);
892 reg[1] = 0;
893 reg[2] = 0;
894 reg[3] = cpu_to_fdt32(0x7);
895 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
896 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
897 fdt_setprop_string(blob, np, "device_type", "pci");
898 fdt_setprop_cell(blob, np, "#address-cells", 3);
899 fdt_setprop_cell(blob, np, "#size-cells", 2);
900 printf(" Added custom interrupt-map for GW16082\n");
901
902 return 0;
903}
904
Tim Harvey77b82a12016-06-17 06:10:42 -0700905/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
906int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
907{
908 char *tmp, *end;
909 char mac[16];
910 unsigned char mac_addr[6];
911 int j;
912
913 sprintf(mac, "eth1addr");
Simon Glass64b723f2017-08-03 12:22:12 -0600914 tmp = env_get(mac);
Tim Harvey77b82a12016-06-17 06:10:42 -0700915 if (tmp) {
916 for (j = 0; j < 6; j++) {
917 mac_addr[j] = tmp ?
918 simple_strtoul(tmp, &end,16) : 0;
919 if (tmp)
920 tmp = (*end) ? end+1 : end;
921 }
922 fdt_setprop(blob, np, "local-mac-address", mac_addr,
923 sizeof(mac_addr));
924 printf(" Added mac addr for eth1\n");
925 return 0;
926 }
927
928 return -1;
929}
930
Tim Harveybfb240a2016-06-17 06:10:41 -0700931/*
932 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
933 * we will walk the PCI bus and add bridge nodes up to the device receiving
934 * the fixup.
935 */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900936void ft_board_pci_fixup(void *blob, struct bd_info *bd)
Tim Harveybfb240a2016-06-17 06:10:41 -0700937{
938 int i, np;
939 struct pci_dev *dev;
940
941 for (i = 0; i < pci_devno; i++) {
942 dev = &pci_devs[i];
943
944 /*
945 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
946 * an EEPROM at i2c1-0x50.
947 */
948 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
949 (dev->device == 0x8240) &&
950 (i2c_set_bus_num(1) == 0) &&
951 (i2c_probe(0x50) == 0))
952 {
953 np = fdt_add_pci_path(blob, dev);
954 if (np > 0)
955 fdt_fixup_gw16082(blob, np, dev);
956 }
Tim Harvey77b82a12016-06-17 06:10:42 -0700957
958 /* ethernet1 mac address */
959 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
960 (dev->device == 0x4380))
961 {
962 np = fdt_add_pci_path(blob, dev);
963 if (np > 0)
964 fdt_fixup_sky2(blob, np, dev);
965 }
Tim Harveybfb240a2016-06-17 06:10:41 -0700966 }
967}
968#endif /* if defined(CONFIG_CMD_PCI) */
Tim Harvey147b5762016-05-24 11:03:59 -0700969
Tim Harvey984aa0d2019-02-04 13:11:00 -0800970void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
Tim Harveyfcabb0b2017-05-15 10:05:07 -0700971{
Tim Harvey984aa0d2019-02-04 13:11:00 -0800972 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
973
974 if (off) {
975 fdt_delprop(blob, off, "ext-reset-output");
976 fdt_delprop(blob, off, "fsl,ext-reset-output");
977 }
Tim Harveyfcabb0b2017-05-15 10:05:07 -0700978}
979
Tim Harvey552c3582014-03-06 07:46:30 -0800980/*
981 * called prior to booting kernel or by 'fdt boardsetup' command
982 *
983 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
984 * - mtd partitions based on mtdparts/mtdids env
985 * - system-serial (board serial num from EEPROM)
986 * - board (full model from EEPROM)
987 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
988 */
Tim Harvey984aa0d2019-02-04 13:11:00 -0800989#define WDOG1_ADDR 0x20bc000
990#define WDOG2_ADDR 0x20c0000
991#define GPIO3_ADDR 0x20a4000
992#define USDHC3_ADDR 0x2198000
993#define PWM0_ADDR 0x2080000
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900994int ft_board_setup(void *blob, struct bd_info *bd)
Tim Harvey552c3582014-03-06 07:46:30 -0800995{
Tim Harvey552c3582014-03-06 07:46:30 -0800996 struct ventana_board_info *info = &ventana_info;
Tim Harvey0da2c522014-08-07 22:35:45 -0700997 struct ventana_eeprom_config *cfg;
Masahiro Yamada20ead6f2018-07-19 16:28:23 +0900998 static const struct node_info nodes[] = {
Tim Harvey552c3582014-03-06 07:46:30 -0800999 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1000 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1001 };
Simon Glass64b723f2017-08-03 12:22:12 -06001002 const char *model = env_get("model");
1003 const char *display = env_get("display");
Tim Harvey16e0eae2015-04-08 12:54:44 -07001004 int i;
1005 char rev = 0;
1006
1007 /* determine board revision */
1008 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1009 if (ventana_info.model[i] >= 'A') {
1010 rev = ventana_info.model[i];
1011 break;
1012 }
1013 }
Tim Harvey552c3582014-03-06 07:46:30 -08001014
Simon Glass64b723f2017-08-03 12:22:12 -06001015 if (env_get("fdt_noauto")) {
Tim Harvey552c3582014-03-06 07:46:30 -08001016 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
Simon Glass2aec3cc2014-10-23 18:58:47 -06001017 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -08001018 }
1019
Tim Harveyc9e43e02015-05-26 11:04:58 -07001020 if (test_bit(EECONFIG_NAND, info->config)) {
1021 /* Update partition nodes using info from mtdparts env var */
1022 puts(" Updating MTD partitions...\n");
1023 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1024 }
Tim Harvey552c3582014-03-06 07:46:30 -08001025
Tim Harveye4af5d32015-04-08 12:54:58 -07001026 /* Update display timings from display env var */
1027 if (display) {
1028 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1029 display) >= 0)
1030 printf(" Set display timings for %s...\n", display);
1031 }
1032
Tim Harvey552c3582014-03-06 07:46:30 -08001033 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1034
1035 /* board serial number */
Simon Glass64b723f2017-08-03 12:22:12 -06001036 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1037 strlen(env_get("serial#")) + 1);
Tim Harvey552c3582014-03-06 07:46:30 -08001038
1039 /* board (model contains model from device-tree) */
1040 fdt_setprop(blob, 0, "board", info->model,
1041 strlen((const char *)info->model) + 1);
1042
Tim Harveycf20e552015-04-08 12:55:01 -07001043 /* set desired digital video capture format */
Simon Glass64b723f2017-08-03 12:22:12 -06001044 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
Tim Harveycf20e552015-04-08 12:55:01 -07001045
Tim Harvey552c3582014-03-06 07:46:30 -08001046 /*
Tim Harveya1d32222016-07-15 07:16:28 -07001047 * Board model specific fixups
Tim Harvey865dc9c2015-04-08 12:54:56 -07001048 */
Tim Harveya1d32222016-07-15 07:16:28 -07001049 switch (board_type) {
1050 case GW51xx:
1051 /*
1052 * disable wdog node for GW51xx-A/B to work around
1053 * errata causing wdog timer to be unreliable.
1054 */
1055 if (rev >= 'A' && rev < 'C') {
Tim Harvey984aa0d2019-02-04 13:11:00 -08001056 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1057 WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001058 if (i)
1059 fdt_status_disabled(blob, i);
1060 }
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001061
1062 /* GW51xx-E adds WDOG1_B external reset */
1063 if (rev < 'E')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001064 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001065 break;
Pushpal Sidhud1100562015-04-08 12:55:00 -07001066
Tim Harveya1d32222016-07-15 07:16:28 -07001067 case GW52xx:
1068 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1069 if (info->model[4] == '2') {
1070 u32 handle = 0;
1071 u32 *range = NULL;
Pushpal Sidhud1100562015-04-08 12:55:00 -07001072
Tim Harveya1d32222016-07-15 07:16:28 -07001073 i = fdt_node_offset_by_compatible(blob, -1,
1074 "fsl,imx6q-pcie");
Pushpal Sidhud1100562015-04-08 12:55:00 -07001075 if (i)
Tim Harveya1d32222016-07-15 07:16:28 -07001076 range = (u32 *)fdt_getprop(blob, i,
1077 "reset-gpio", NULL);
1078
1079 if (range) {
Tim Harvey984aa0d2019-02-04 13:11:00 -08001080 i = fdt_node_offset_by_compat_reg(blob,
1081 "fsl,imx6q-gpio", GPIO3_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001082 if (i)
1083 handle = fdt_get_phandle(blob, i);
1084 if (handle) {
1085 range[0] = cpu_to_fdt32(handle);
1086 range[1] = cpu_to_fdt32(23);
1087 }
Pushpal Sidhud1100562015-04-08 12:55:00 -07001088 }
Tim Harveya1d32222016-07-15 07:16:28 -07001089
1090 /* these have broken usd_vsel */
1091 if (strstr((const char *)info->model, "SP318-B") ||
1092 strstr((const char *)info->model, "SP331-B"))
1093 gpio_cfg[board_type].usd_vsel = 0;
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001094
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001095 /* GW522x-B adds WDOG1_B external reset */
Tim Harvey984aa0d2019-02-04 13:11:00 -08001096 if (rev < 'B')
1097 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Pushpal Sidhud1100562015-04-08 12:55:00 -07001098 }
Tim Harveydc5996a2017-05-15 10:05:06 -07001099
1100 /* GW520x-E adds WDOG1_B external reset */
1101 else if (info->model[4] == '0' && rev < 'E')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001102 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001103 break;
Tim Harvey147b5762016-05-24 11:03:59 -07001104
Tim Harveya1d32222016-07-15 07:16:28 -07001105 case GW53xx:
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001106 /* GW53xx-E adds WDOG1_B external reset */
1107 if (rev < 'E')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001108 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001109 break;
Pushpal Sidhud1100562015-04-08 12:55:00 -07001110
Tim Harveya1d32222016-07-15 07:16:28 -07001111 case GW54xx:
1112 /*
1113 * disable serial2 node for GW54xx for compatibility with older
1114 * 3.10.x kernel that improperly had this node enabled in the DT
1115 */
Tim Harvey984aa0d2019-02-04 13:11:00 -08001116 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1117 0);
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001118
1119 /* GW54xx-E adds WDOG2_B external reset */
1120 if (rev < 'E')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001121 ft_board_wdog_fixup(blob, WDOG2_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001122 break;
1123
1124 case GW551x:
1125 /*
1126 * isolate CSI0_DATA_EN for GW551x-A to work around errata
1127 * causing non functional digital video in (it is not hooked up)
1128 */
1129 if (rev == 'A') {
1130 u32 *range = NULL;
1131 int len;
1132 const u32 *handle = NULL;
1133
1134 i = fdt_node_offset_by_compatible(blob, -1,
1135 "fsl,imx-tda1997x-video");
1136 if (i)
1137 handle = fdt_getprop(blob, i, "pinctrl-0",
1138 NULL);
1139 if (handle)
1140 i = fdt_node_offset_by_phandle(blob,
1141 fdt32_to_cpu(*handle));
1142 if (i)
1143 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1144 &len);
1145 if (range) {
1146 len /= sizeof(u32);
1147 for (i = 0; i < len; i += 6) {
1148 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1149 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1150 /* mux PAD_CSI0_DATA_EN to GPIO */
1151 if (is_cpu_type(MXC_CPU_MX6Q) &&
1152 mux_reg == 0x260 &&
1153 conf_reg == 0x630)
1154 range[i+3] = cpu_to_fdt32(0x5);
1155 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1156 mux_reg == 0x08c &&
1157 conf_reg == 0x3a0)
1158 range[i+3] = cpu_to_fdt32(0x5);
1159 }
1160 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1161 len);
Tim Harvey6944ccf2015-04-08 12:54:53 -07001162 }
Tim Harveydc8b5e62015-04-08 12:55:02 -07001163
Tim Harveya1d32222016-07-15 07:16:28 -07001164 /* set BT656 video format */
1165 ft_sethdmiinfmt(blob, "yuv422bt656");
1166 }
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001167
1168 /* GW551x-C adds WDOG1_B external reset */
1169 if (rev < 'C')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001170 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001171 break;
Tim Harvey5852a332019-02-04 13:10:58 -08001172 case GW5901:
1173 case GW5902:
1174 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1175 if (rev < 'B')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001176 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harvey5852a332019-02-04 13:10:58 -08001177 break;
Tim Harvey6944ccf2015-04-08 12:54:53 -07001178 }
1179
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001180 /* Configure DIO */
Tim Harvey41595b52016-07-15 07:14:23 -07001181 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001182 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1183 char arg[10];
1184
1185 sprintf(arg, "dio%d", i);
1186 if (!hwconfig(arg))
1187 continue;
1188 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1189 {
Tim Harvey984aa0d2019-02-04 13:11:00 -08001190 phys_addr_t addr;
1191 int off;
1192
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001193 printf(" Enabling pwm%d for DIO%d\n",
1194 cfg->pwm_param, i);
Tim Harvey984aa0d2019-02-04 13:11:00 -08001195 addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1196 off = fdt_node_offset_by_compat_reg(blob,
1197 "fsl,imx6q-pwm",
1198 addr);
1199 if (off)
1200 fdt_status_okay(blob, off);
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001201 }
1202 }
1203
Tim Harvey147b5762016-05-24 11:03:59 -07001204 /* remove no-1-8-v if UHS-I support is present */
1205 if (gpio_cfg[board_type].usd_vsel) {
1206 debug("Enabling UHS-I support\n");
Tim Harvey984aa0d2019-02-04 13:11:00 -08001207 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1208 USDHC3_ADDR);
1209 if (i)
1210 fdt_delprop(blob, i, "no-1-8-v");
Tim Harvey147b5762016-05-24 11:03:59 -07001211 }
1212
Tim Harveybfb240a2016-06-17 06:10:41 -07001213#if defined(CONFIG_CMD_PCI)
Simon Glass64b723f2017-08-03 12:22:12 -06001214 if (!env_get("nopcifixup"))
Tim Harveybfb240a2016-06-17 06:10:41 -07001215 ft_board_pci_fixup(blob, bd);
1216#endif
1217
Tim Harvey6944ccf2015-04-08 12:54:53 -07001218 /*
Tim Harvey552c3582014-03-06 07:46:30 -08001219 * Peripheral Config:
1220 * remove nodes by alias path if EEPROM config tells us the
1221 * peripheral is not loaded on the board.
1222 */
Simon Glass64b723f2017-08-03 12:22:12 -06001223 if (env_get("fdt_noconfig")) {
Tim Harvey0da2c522014-08-07 22:35:45 -07001224 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
Simon Glass2aec3cc2014-10-23 18:58:47 -06001225 return 0;
Tim Harvey0da2c522014-08-07 22:35:45 -07001226 }
1227 cfg = econfig;
1228 while (cfg->name) {
1229 if (!test_bit(cfg->bit, info->config)) {
1230 fdt_del_node_and_alias(blob, cfg->dtalias ?
1231 cfg->dtalias : cfg->name);
1232 }
1233 cfg++;
Tim Harvey552c3582014-03-06 07:46:30 -08001234 }
Simon Glass2aec3cc2014-10-23 18:58:47 -06001235
1236 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -08001237}
Robert P. J. Day3c757002016-05-19 15:23:12 -04001238#endif /* CONFIG_OF_BOARD_SETUP */