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git01.mediatek.com / filogic / uboot / 7359cc2e01d56095b764f22ea5ee61799581c61d / . / arch / arm / dts / cat875.dtsi
blob: 8c9da8b4bd60bf325ebcd02e70904701e0f97428 [file] [log] [blame]
Lad Prabhakarb4b65ec2021-03-15 22:24:05 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
4 *
Marek Vasut2a8450f2023-01-26 21:01:32 +0100[diff] [blame]5 * Copyright (C) 2019 Renesas Electronics Corp.
Lad Prabhakarb4b65ec2021-03-15 22:24:05 +0000[diff] [blame]6 */
7
8/ {
9 model = "Silicon Linux sub board for CAT874 (CAT875)";
10
11 aliases {
12 ethernet0 = &avb;
13 };
14};
15
16&avb {
17 pinctrl-0 = <&avb_pins>;
18 pinctrl-names = "default";
19 renesas,no-ether-link;
20 phy-handle = <&phy0>;
Marek Vasut2a8450f2023-01-26 21:01:32 +0100[diff] [blame]21 phy-mode = "rgmii-id";
Lad Prabhakarb4b65ec2021-03-15 22:24:05 +0000[diff] [blame]22 status = "okay";
23
24 phy0: ethernet-phy@0 {
Marek Vasut2a8450f2023-01-26 21:01:32 +0100[diff] [blame]25 compatible = "ethernet-phy-id001c.c915",
26 "ethernet-phy-ieee802.3-c22";
Lad Prabhakarb4b65ec2021-03-15 22:24:05 +0000[diff] [blame]27 reg = <0>;
28 interrupt-parent = <&gpio2>;
29 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
30 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
31 };
32};
33
34&can0 {
35 pinctrl-0 = <&can0_pins>;
36 pinctrl-names = "default";
37 status = "okay";
38};
39
40&can1 {
41 pinctrl-0 = <&can1_pins>;
42 pinctrl-names = "default";
43 status = "okay";
44};
45
46&pciec0 {
47 status = "okay";
48};
49
50&pfc {
51 avb_pins: avb {
52 mux {
53 groups = "avb_mii";
54 function = "avb";
55 };
56 };
57
58 can0_pins: can0 {
59 groups = "can0_data";
60 function = "can0";
61 };
62
63 can1_pins: can1 {
64 groups = "can1_data";
65 function = "can1";
66 };
67};