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git01.mediatek.com / filogic / uboot / 734d57703a3358d242b5deca7faae37960c656d1 / . / arch / arm / dts / imx8mm-tqma8mqml.dtsi
blob: f649dfacb4b696caef22fc9e17a2d55cc20fb8e0 [file] [log] [blame]
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7#include "imx8mm.dtsi"
8
9/ {
10 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";
11 compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
12
13 memory@40000000 {
14 device_type = "memory";
15 /* our minimum RAM config will be 1024 MiB */
16 reg = <0x00000000 0x40000000 0 0x40000000>;
17 };
18
19 /* e-MMC IO, needed for HS modes */
20 reg_vcc1v8: regulator-vcc1v8 {
21 compatible = "regulator-fixed";
22 regulator-name = "TQMA8MXML_VCC1V8";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <1800000>;
25 };
26
27 /* identical to buck4_reg, but should never change */
28 reg_vcc3v3: regulator-vcc3v3 {
29 compatible = "regulator-fixed";
30 regulator-name = "TQMA8MXML_VCC3V3";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 };
34
35 reserved-memory {
36 #address-cells = <2>;
37 #size-cells = <2>;
38 ranges;
39
40 /* global autoconfigured region for contiguous allocations */
41 linux,cma {
42 compatible = "shared-dma-pool";
43 reusable;
44 /* 640 MiB */
45 size = <0 0x28000000>;
46 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
47 alloc-ranges = <0 0x40000000 0 0x78000000>;
48 linux,cma-default;
49 };
50 };
51};
52
53&A53_0 {
54 cpu-supply = <&buck2_reg>;
55};
56
57&flexspi {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_flexspi>;
60 status = "okay";
61
62 flash0: flash@0 {
63 compatible = "jedec,spi-nor";
64 reg = <0>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67 spi-max-frequency = <84000000>;
68 spi-tx-bus-width = <1>;
69 spi-rx-bus-width = <4>;
70 };
71};
72
73&gpu_2d {
74 status = "okay";
75};
76
77&gpu_3d {
78 status = "okay";
79};
80
81&i2c1 {
82 clock-frequency = <100000>;
83 pinctrl-names = "default", "gpio";
84 pinctrl-0 = <&pinctrl_i2c1>;
85 pinctrl-1 = <&pinctrl_i2c1_gpio>;
86 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
87 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
88 status = "okay";
89
90 sensor0: temperature-sensor-eeprom@1b {
91 compatible = "nxp,se97", "jedec,jc-42.4-temp";
92 reg = <0x1b>;
93 };
94
95 pca9450: pmic@25 {
96 compatible = "nxp,pca9450a";
97 reg = <0x25>;
98
99 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
100 pinctrl-0 = <&pinctrl_pmic>;
101 pinctrl-names = "default";
102 interrupt-parent = <&gpio1>;
103 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
104
105 regulators {
106 /* V_0V85_SOC: 0.85 */
107 buck1_reg: BUCK1 {
108 regulator-name = "BUCK1";
109 regulator-min-microvolt = <850000>;
110 regulator-max-microvolt = <850000>;
111 regulator-boot-on;
112 regulator-always-on;
113 regulator-ramp-delay = <3125>;
114 };
115
116 /* VDD_ARM */
117 buck2_reg: BUCK2 {
118 regulator-name = "BUCK2";
119 regulator-min-microvolt = <850000>;
120 regulator-max-microvolt = <1000000>;
121 regulator-boot-on;
122 regulator-always-on;
123 nxp,dvs-run-voltage = <950000>;
124 nxp,dvs-standby-voltage = <850000>;
125 regulator-ramp-delay = <3125>;
126 };
127
128 /* V_0V85_GPU / DRAM / VPU */
129 buck3_reg: BUCK3 {
130 regulator-name = "BUCK3";
131 regulator-min-microvolt = <850000>;
132 regulator-max-microvolt = <950000>;
133 regulator-boot-on;
134 regulator-always-on;
135 regulator-ramp-delay = <3125>;
136 };
137
138 /* VCC3V3 -> VMMC, ... must not be changed */
139 buck4_reg: BUCK4 {
140 regulator-name = "BUCK4";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
143 regulator-boot-on;
144 regulator-always-on;
145 };
146
147 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
148 buck5_reg: BUCK5 {
149 regulator-name = "BUCK5";
150 regulator-min-microvolt = <1800000>;
151 regulator-max-microvolt = <1800000>;
152 regulator-boot-on;
153 regulator-always-on;
154 };
155
156 /* V_1V1 -> RAM, ... must not be changed */
157 buck6_reg: BUCK6 {
158 regulator-name = "BUCK6";
159 regulator-min-microvolt = <1100000>;
160 regulator-max-microvolt = <1100000>;
161 regulator-boot-on;
162 regulator-always-on;
163 };
164
165 /* V_1V8_SNVS */
166 ldo1_reg: LDO1 {
167 regulator-name = "LDO1";
168 regulator-min-microvolt = <1800000>;
169 regulator-max-microvolt = <1800000>;
170 regulator-boot-on;
171 regulator-always-on;
172 };
173
174 /* V_0V8_SNVS */
175 ldo2_reg: LDO2 {
176 regulator-name = "LDO2";
177 regulator-min-microvolt = <800000>;
178 regulator-max-microvolt = <850000>;
179 regulator-boot-on;
180 regulator-always-on;
181 };
182
183 /* V_1V8_ANA */
184 ldo3_reg: LDO3 {
185 regulator-name = "LDO3";
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <1800000>;
188 regulator-boot-on;
189 regulator-always-on;
190 };
191
192 /* V_0V9_MIPI */
193 ldo4_reg: LDO4 {
194 regulator-name = "LDO4";
195 regulator-min-microvolt = <900000>;
196 regulator-max-microvolt = <900000>;
197 regulator-boot-on;
198 regulator-always-on;
199 };
200
201 /* VCC SD IO - switched using SD2 VSELECT */
202 ldo5_reg: LDO5 {
203 regulator-name = "LDO5";
204 regulator-min-microvolt = <1800000>;
205 regulator-max-microvolt = <3300000>;
206 };
207 };
208 };
209
210
211 pcf85063: rtc@51 {
212 compatible = "nxp,pcf85063a";
213 reg = <0x51>;
214 quartz-load-femtofarads = <7000>;
215 };
216
217 eeprom1: eeprom@53 {
218 compatible = "nxp,se97b", "atmel,24c02";
219 read-only;
220 reg = <0x53>;
221 pagesize = <16>;
222 };
223
224 eeprom0: eeprom@57 {
225 compatible = "atmel,24c64";
226 reg = <0x57>;
227 pagesize = <32>;
228 };
229};
230
231&pcie_phy {
232 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
233 fsl,clkreq-unsupported;
234};
235
236&usdhc3 {
237 pinctrl-names = "default", "state_100mhz", "state_200mhz";
238 pinctrl-0 = <&pinctrl_usdhc3>;
239 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
240 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
241 bus-width = <8>;
242 non-removable;
243 no-sd;
244 no-sdio;
245 vmmc-supply = <&reg_vcc3v3>;
246 vqmmc-supply = <&reg_vcc1v8>;
247 status = "okay";
248};
249
250/*
251 * Attention:
252 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
253 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
254 */
255&wdog1 {
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_wdog>;
258 fsl,ext-reset-output;
259 status = "okay";
260};
261
262&iomuxc {
263 pinctrl_flexspi: flexspigrp {
264 fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>,
265 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
266 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>,
267 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>,
268 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>,
269 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>;
270 };
271
272 pinctrl_i2c1: i2c1grp {
273 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>,
274 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>;
275 };
276
277 pinctrl_i2c1_gpio: i2c1gpiogrp {
278 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>,
279 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>;
280 };
281
282 pinctrl_pmic: pmicgrp {
283 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>;
284 };
285
286 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
287 fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
288 };
289
290 pinctrl_usdhc3: usdhc3grp {
291 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
292 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
293 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
294 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
295 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
296 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
297 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
298 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
299 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
300 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
301 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
302 /* option USDHC3_RESET_B not defined, only in RM */
303 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
304 };
305
306 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
307 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
308 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
309 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
310 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
311 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
312 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
313 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
314 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
315 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
316 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
317 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
318 /* option USDHC3_RESET_B not defined, only in RM */
319 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
320 };
321
322 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
323 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
324 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
325 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
326 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
327 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
328 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
329 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
330 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
331 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
332 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
333 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
334 /* option USDHC3_RESET_B not defined, only in RM */
335 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
336 };
337
338 pinctrl_wdog: wdoggrp {
339 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;
340 };
341};