Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/io.h> |
| 8 | #include <asm/arch/imx-regs.h> |
| 9 | #include <asm/arch/siul.h> |
| 10 | #include <asm/arch/lpddr2.h> |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <mmc.h> |
Yangbo Lu | 7334038 | 2019-06-21 11:42:28 +0800 | [diff] [blame^] | 13 | #include <fsl_esdhc_imx.h> |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 14 | #include <miiphy.h> |
| 15 | #include <netdev.h> |
| 16 | #include <i2c.h> |
| 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
| 20 | void setup_iomux_ddr(void) |
| 21 | { |
| 22 | lpddr2_config_iomux(DDR0); |
| 23 | lpddr2_config_iomux(DDR1); |
| 24 | |
| 25 | } |
| 26 | |
| 27 | void ddr_phy_init(void) |
| 28 | { |
| 29 | } |
| 30 | |
| 31 | void ddr_ctrl_init(void) |
| 32 | { |
| 33 | config_mmdc(0); |
| 34 | config_mmdc(1); |
| 35 | } |
| 36 | |
| 37 | int dram_init(void) |
| 38 | { |
| 39 | setup_iomux_ddr(); |
| 40 | |
| 41 | ddr_ctrl_init(); |
| 42 | |
| 43 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | |
| 48 | static void setup_iomux_uart(void) |
| 49 | { |
| 50 | /* Muxing for linflex */ |
| 51 | /* Replace the magic values after bringup */ |
| 52 | |
| 53 | /* set TXD - MSCR[12] PA12 */ |
| 54 | writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD)); |
| 55 | |
| 56 | /* set RXD - MSCR[11] - PA11 */ |
| 57 | writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD)); |
| 58 | |
| 59 | /* set RXD - IMCR[200] - 200 */ |
| 60 | writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD)); |
| 61 | } |
| 62 | |
| 63 | static void setup_iomux_enet(void) |
| 64 | { |
| 65 | } |
| 66 | |
| 67 | static void setup_iomux_i2c(void) |
| 68 | { |
| 69 | } |
| 70 | |
| 71 | #ifdef CONFIG_SYS_USE_NAND |
| 72 | void setup_iomux_nfc(void) |
| 73 | { |
| 74 | } |
| 75 | #endif |
| 76 | |
Yangbo Lu | 7334038 | 2019-06-21 11:42:28 +0800 | [diff] [blame^] | 77 | #ifdef CONFIG_FSL_ESDHC_IMX |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 78 | struct fsl_esdhc_cfg esdhc_cfg[1] = { |
| 79 | {USDHC_BASE_ADDR}, |
| 80 | }; |
| 81 | |
| 82 | int board_mmc_getcd(struct mmc *mmc) |
| 83 | { |
| 84 | /* eSDHC1 is always present */ |
| 85 | return 1; |
| 86 | } |
| 87 | |
| 88 | int board_mmc_init(bd_t * bis) |
| 89 | { |
| 90 | esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); |
| 91 | |
| 92 | /* Set iomux PADS for USDHC */ |
| 93 | |
| 94 | /* PK6 pad: uSDHC clk */ |
| 95 | writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150)); |
| 96 | writel(0x3, SIUL2_MSCRn(902)); |
| 97 | |
| 98 | /* PK7 pad: uSDHC CMD */ |
| 99 | writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151)); |
| 100 | writel(0x3, SIUL2_MSCRn(901)); |
| 101 | |
| 102 | /* PK8 pad: uSDHC DAT0 */ |
| 103 | writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152)); |
| 104 | writel(0x3, SIUL2_MSCRn(903)); |
| 105 | |
| 106 | /* PK9 pad: uSDHC DAT1 */ |
| 107 | writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153)); |
| 108 | writel(0x3, SIUL2_MSCRn(904)); |
| 109 | |
| 110 | /* PK10 pad: uSDHC DAT2 */ |
| 111 | writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154)); |
| 112 | writel(0x3, SIUL2_MSCRn(905)); |
| 113 | |
| 114 | /* PK11 pad: uSDHC DAT3 */ |
| 115 | writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155)); |
| 116 | writel(0x3, SIUL2_MSCRn(906)); |
| 117 | |
| 118 | /* PK15 pad: uSDHC DAT4 */ |
| 119 | writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159)); |
| 120 | writel(0x3, SIUL2_MSCRn(907)); |
| 121 | |
| 122 | /* PL0 pad: uSDHC DAT5 */ |
| 123 | writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160)); |
| 124 | writel(0x3, SIUL2_MSCRn(908)); |
| 125 | |
| 126 | /* PL1 pad: uSDHC DAT6 */ |
| 127 | writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161)); |
| 128 | writel(0x3, SIUL2_MSCRn(909)); |
| 129 | |
| 130 | /* PL2 pad: uSDHC DAT7 */ |
| 131 | writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162)); |
| 132 | writel(0x3, SIUL2_MSCRn(910)); |
| 133 | |
| 134 | return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
| 135 | } |
| 136 | #endif |
| 137 | |
| 138 | static void mscm_init(void) |
| 139 | { |
| 140 | struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; |
| 141 | int i; |
| 142 | |
| 143 | for (i = 0; i < MSCM_IRSPRC_NUM; i++) |
| 144 | writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]); |
| 145 | } |
| 146 | |
| 147 | int board_phy_config(struct phy_device *phydev) |
| 148 | { |
| 149 | if (phydev->drv->config) |
| 150 | phydev->drv->config(phydev); |
| 151 | |
| 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | int board_early_init_f(void) |
| 156 | { |
| 157 | clock_init(); |
| 158 | mscm_init(); |
| 159 | |
| 160 | setup_iomux_uart(); |
| 161 | setup_iomux_enet(); |
| 162 | setup_iomux_i2c(); |
| 163 | #ifdef CONFIG_SYS_USE_NAND |
| 164 | setup_iomux_nfc(); |
| 165 | #endif |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | int board_init(void) |
| 170 | { |
| 171 | /* address of boot parameters */ |
| 172 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | int checkboard(void) |
| 178 | { |
| 179 | puts("Board: s32v234evb\n"); |
| 180 | |
| 181 | return 0; |
| 182 | } |