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git01.mediatek.com / filogic / uboot / 730fcb5c7c49c12afe7675f136cca54455fdf0f2 / . / configs / nanopi-r5c-rk3568_defconfig
blob: 4a43b17ccb16cdf0aa5e36c30f51fb4aaecb71aa [file] [log] [blame]
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT=y
Jonas Karlmanac800512023-08-02 19:59:33 +0000[diff] [blame]3CONFIG_SYS_HAS_NONCACHED_MEMORY=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]4CONFIG_COUNTER_FREQUENCY=24000000
5CONFIG_ARCH_ROCKCHIP=y
Jonas Karlman737739e2024-05-04 19:43:00 +0000[diff] [blame]6CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-nanopi-r5c"
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]7CONFIG_ROCKCHIP_RK3568=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]8CONFIG_SPL_SERIAL=y
Tom Rinic427a582024-10-08 09:18:32 -0600[diff] [blame]9CONFIG_SYS_LOAD_ADDR=0xc00800
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]10CONFIG_DEBUG_UART_BASE=0xFE660000
11CONFIG_DEBUG_UART_CLOCK=24000000
Jonas Karlmanac800512023-08-02 19:59:33 +0000[diff] [blame]12CONFIG_PCI=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]13CONFIG_DEBUG_UART=y
14CONFIG_FIT=y
15CONFIG_FIT_VERBOSE=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame]16CONFIG_SPL_FIT_SIGNATURE=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]17CONFIG_SPL_LOAD_FIT=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame]18CONFIG_LEGACY_IMAGE_FORMAT=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]19CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
20# CONFIG_DISPLAY_CPUINFO is not set
21CONFIG_DISPLAY_BOARDINFO_LATE=y
22CONFIG_SPL_MAX_SIZE=0x40000
23CONFIG_SPL_PAD_TO=0x7f8000
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]24# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]25CONFIG_SPL_ATF=y
26CONFIG_CMD_GPIO=y
27CONFIG_CMD_GPT=y
28CONFIG_CMD_I2C=y
29CONFIG_CMD_MMC=y
Jonas Karlmanac800512023-08-02 19:59:33 +0000[diff] [blame]30CONFIG_CMD_PCI=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]31CONFIG_CMD_USB=y
32CONFIG_CMD_PMIC=y
33CONFIG_CMD_REGULATOR=y
34# CONFIG_SPL_DOS_PARTITION is not set
35CONFIG_SPL_OF_CONTROL=y
36CONFIG_OF_LIVE=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame]37CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame]38CONFIG_SPL_DM_SEQ_ALIAS=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]39CONFIG_SPL_REGMAP=y
40CONFIG_SPL_SYSCON=y
41CONFIG_SPL_CLK=y
42CONFIG_ROCKCHIP_GPIO=y
43CONFIG_SYS_I2C_ROCKCHIP=y
44CONFIG_MISC=y
45CONFIG_SUPPORT_EMMC_RPMB=y
46CONFIG_MMC_DW=y
47CONFIG_MMC_DW_ROCKCHIP=y
48CONFIG_MMC_SDHCI=y
49CONFIG_MMC_SDHCI_SDMA=y
50CONFIG_MMC_SDHCI_ROCKCHIP=y
Jonas Karlmanac800512023-08-02 19:59:33 +0000[diff] [blame]51CONFIG_RTL8169=y
52CONFIG_PCIE_DW_ROCKCHIP=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]53CONFIG_PHY_ROCKCHIP_INNO_USB2=y
54CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
Jonas Karlman6c8ecef2023-08-02 19:49:46 +0000[diff] [blame]55CONFIG_SPL_PINCTRL=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]56CONFIG_DM_PMIC=y
57CONFIG_PMIC_RK8XX=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]58CONFIG_REGULATOR_RK8XX=y
59CONFIG_PWM_ROCKCHIP=y
60CONFIG_SPL_RAM=y
61CONFIG_BAUDRATE=1500000
62CONFIG_DEBUG_UART_SHIFT=2
63CONFIG_SYS_NS16550_MEM32=y
64CONFIG_SYSRESET=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]65CONFIG_USB=y
66CONFIG_USB_XHCI_HCD=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]67CONFIG_USB_EHCI_HCD=y
68CONFIG_USB_EHCI_GENERIC=y
69CONFIG_USB_OHCI_HCD=y
70CONFIG_USB_OHCI_GENERIC=y
71CONFIG_USB_DWC3=y
Jonas Karlmand0de5dc2023-07-30 22:59:59 +0000[diff] [blame]72CONFIG_USB_DWC3_GENERIC=y
Tianling Shen865fd9a2023-05-30 15:11:22 +0800[diff] [blame]73CONFIG_ERRNO_STR=y