Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _CONFIG_SYNOLOGY_DS414_H |
| 7 | #define _CONFIG_SYNOLOGY_DS414_H |
| 8 | |
| 9 | /* |
| 10 | * High Level Configuration Options (easy to change) |
| 11 | */ |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 12 | |
| 13 | /* |
| 14 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
| 15 | * for DDR ECC byte filling in the SPL before loading the main |
| 16 | * U-Boot into it. |
| 17 | */ |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 18 | |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 19 | /* I2C */ |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 20 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 21 | |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 22 | /* PCIe support */ |
| 23 | #ifndef CONFIG_SPL_BUILD |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 24 | #define CONFIG_PCI_SCAN_SHOW |
| 25 | #endif |
| 26 | |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 27 | /* |
| 28 | * mv-common.h should be defined after CMD configs since it used them |
| 29 | * to enable certain macros |
| 30 | */ |
| 31 | #include "mv-common.h" |
| 32 | |
| 33 | /* |
| 34 | * Memory layout while starting into the bin_hdr via the |
| 35 | * BootROM: |
| 36 | * |
| 37 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) |
| 38 | * 0x4000.4030 bin_hdr start address |
| 39 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) |
| 40 | * 0x4007.fffc BootROM stack top |
| 41 | * |
| 42 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in |
| 43 | * L2 cache thus cannot be used. |
| 44 | */ |
| 45 | |
| 46 | /* SPL */ |
| 47 | /* Defines for SPL */ |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 48 | #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) |
| 49 | |
| 50 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) |
| 51 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
| 52 | |
| 53 | #ifdef CONFIG_SPL_BUILD |
| 54 | #define CONFIG_SYS_MALLOC_SIMPLE |
| 55 | #endif |
| 56 | |
| 57 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) |
| 58 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
| 59 | |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 60 | /* Default Environment */ |
Phil Sutter | ef534b2 | 2021-03-07 22:22:27 +0100 | [diff] [blame] | 61 | #define CONFIG_BOOTCOMMAND \ |
| 62 | "sf probe; " \ |
| 63 | "sf read ${loadaddr} 0xd0000 0x2d0000; " \ |
| 64 | "sf read ${ramdisk_addr_r} 0x3a0000 0x430000; " \ |
| 65 | "bootm ${loadaddr} ${ramdisk_addr_r}" |
| 66 | |
| 67 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 68 | "initrd_high=0xffffffff\0" \ |
| 69 | "ramdisk_addr_r=0x8000000\0" \ |
| 70 | "usb0Mode=host\0usb1Mode=host\0usb2Mode=device\0" \ |
Phil Sutter | 6d1bcbf | 2021-03-05 21:05:45 +0100 | [diff] [blame] | 71 | "ethmtu=1500\0eth1mtu=1500\0" \ |
| 72 | "update_uboot=sf probe; dhcp; " \ |
| 73 | "mw.b ${loadaddr} 0x0 0xd0000; " \ |
| 74 | "tftpboot ${loadaddr} u-boot-spl.kwb; " \ |
| 75 | "sf update ${loadaddr} 0x0 0xd0000\0" |
| 76 | |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 77 | |
Phil Sutter | 246a61f | 2021-01-03 23:06:44 +0100 | [diff] [blame] | 78 | /* increase autoneg timeout, my NIC sucks */ |
| 79 | #define PHY_ANEG_TIMEOUT 16000 |
| 80 | |
Phil Sutter | d76eba6 | 2015-12-25 14:41:25 +0100 | [diff] [blame] | 81 | #endif /* _CONFIG_SYNOLOGY_DS414_H */ |