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git01.mediatek.com / filogic / uboot / 721625288c76ccd65579ec229b418afa4178d1f1 / . / arch / powerpc / dts / km8321.dtsi
blob: 6c360175630d6eda4f3eda410ecf06b795ca190c [file] [log] [blame]
Heiko Schocher3c521072020-02-03 07:43:57 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Holger Brunck72162522020-10-08 12:27:22 +0200[diff] [blame^]3 * Hitachi Power Grids km8321 common ports Device Tree Source
Heiko Schocher3c521072020-02-03 07:43:57 +0100[diff] [blame]4 *
5 * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
6 *
7 */
8
9/dts-v1/;
10
11/ {
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 PowerPC,8321@0 {
17 device_type = "cpu";
18 reg = <0x0>;
19 d-cache-line-size = <32>; // 32 bytes
20 i-cache-line-size = <32>; // 32 bytes
21 d-cache-size = <16384>; // L1, 16K
22 i-cache-size = <16384>; // L1, 16K
23 timebase-frequency = <66000000>;
24 bus-frequency = <264000000>;
25 clock-frequency = <528000000>;
26 };
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x00000000 0x10000000>;
32 };
33
34 soc: soc8321@e0000000 {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 device_type = "soc";
38 compatible = "simple-bus";
39 ranges = <0x0 0xe0000000 0x00100000>;
40 reg = <0xe0000000 0x00000200>;
41 bus-frequency = <264000000>;
42
43 i2c0: i2c@3000 {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cell-index = <0>;
47 compatible = "fsl,mpc8313-i2c","fsl-i2c";
48 reg = <0x3000 0x100>;
49 interrupts = <14 0x8>;
50 interrupt-parent = <&ipic>;
51 clock-frequency = <100000>;
52 };
53
54 serial0: serial@4500 {
55 cell-index = <0>;
56 device_type = "serial";
57 compatible = "fsl,ns16550", "ns16550";
58 reg = <0x4500 0x100>;
59 clock-frequency = <264000000>;
60 interrupts = <9 0x8>;
61 interrupt-parent = <&ipic>;
62 };
63
64 dma@82a8 {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
68 reg = <0x82a8 4>;
69 ranges = <0 0x8100 0x1a8>;
70 interrupt-parent = <&ipic>;
71 interrupts = <71 8>;
72 cell-index = <0>;
73 dma-channel@0 {
74 compatible = "fsl,mpc8321-dma-channel",
75 "fsl,elo-dma-channel";
76 reg = <0 0x80>;
77 interrupt-parent = <&ipic>;
78 interrupts = <71 8>;
79 };
80 dma-channel@80 {
81 compatible = "fsl,mpc8321-dma-channel",
82 "fsl,elo-dma-channel";
83 reg = <0x80 0x80>;
84 interrupt-parent = <&ipic>;
85 interrupts = <71 8>;
86 };
87 dma-channel@100 {
88 compatible = "fsl,mpc8321-dma-channel",
89 "fsl,elo-dma-channel";
90 reg = <0x100 0x80>;
91 interrupt-parent = <&ipic>;
92 interrupts = <71 8>;
93 };
94 dma-channel@180 {
95 compatible = "fsl,mpc8321-dma-channel",
96 "fsl,elo-dma-channel";
97 reg = <0x180 0x28>;
98 interrupt-parent = <&ipic>;
99 interrupts = <71 8>;
100 };
101 };
102
103 ipic: pic@700 {
104 #address-cells = <0>;
105 #interrupt-cells = <2>;
106 compatible = "fsl,pq2pro-pic", "fsl,ipic";
107 interrupt-controller;
108 reg = <0x700 0x100>;
109 device_type = "ipic";
110 };
111
112 par_io: par_io@1400 {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x1400 0x100>;
116 ranges;
117 device_type = "par_io";
118 num-ports = <7>;
119
120 qe_pio_d: gpio-controller@48 {
121 #gpio-cells = <2>;
122 compatible = "fsl,mpc8360-qe-pario-bank",
123 "fsl,mpc8323-qe-pario-bank";
124 reg = <0x1448 0x18>;
125 gpio-controller;
126 };
127 };
128 };
129
130 qe: qe@e0100000 {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 device_type = "qe";
134 compatible = "fsl,qe";
135 ranges = <0x0 0xe0100000 0x00100000>;
136 reg = <0xe0100000 0x480>;
137 brg-frequency = <0>;
138 bus-frequency = <396000000>;
139
140 muram@10000 {
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "fsl,qe-muram", "fsl,cpm-muram";
144 ranges = <0x0 0x00010000 0x00004000>;
145
146 data-only@0 {
147 compatible = "fsl,qe-muram-data",
148 "fsl,cpm-muram-data";
149 reg = <0x0 0x4000>;
150 };
151 };
152
153 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
154 enet_piggy2: ucc@3200 {
155 device_type = "network";
156 compatible = "ucc_geth";
157 cell-index = <4>;
158 reg = <0x3200 0x200>;
159 interrupts = <35>;
160 interrupt-parent = <&qeic>;
161 local-mac-address = [ 00 00 00 00 00 00 ];
162 rx-clock-name = "none";
163 tx-clock-name = "clk17";
164 phy-handle = <&phy_piggy2>;
165 phy-connection-type = "rmii";
166 pio-handle = <&pio_ucc4>;
167 };
168
169 mdio: mdio@3320 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg = <0x3320 0x18>;
173 compatible = "fsl,ucc-mdio";
174
175 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
176 phy_piggy2: ethernet-phy@00 {
177 reg = <0x0>;
178 device_type = "ethernet-phy";
179 };
180 };
181
182 qeic: interrupt-controller@80 {
183 interrupt-controller;
184 compatible = "fsl,qe-ic";
185 #address-cells = <0>;
186 #interrupt-cells = <1>;
187 reg = <0x80 0x80>;
188 big-endian;
189 interrupts = <32 8 33 8>;
190 interrupt-parent = <&ipic>;
191 };
192 bootcount@0x13ff8 {
193 device_type = "bootcount";
194 compatible = "u-boot,bootcount";
195 reg = <0x13ff8 0x08>;
196 };
197
198 spi0: spi@4c0 {
199 cell-index = <0>;
200 compatible = "fsl,spi";
201 reg = <0x4c0 0x40>;
202 interrupts = <2>;
203 interrupt-parent = <&qeic>;
204 mode = "qe";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 pio-handle = <&pio_spi>;
208 };
209 };
210
211 localbus: localbus@e0005000 {
212 #address-cells = <2>;
213 #size-cells = <1>;
214 compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus",
215 "simple-bus";
216 reg = <0xe0005000 0xd8>;
217 };
218};
219
220#include "km8321-uboot.dtsi"