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git01.mediatek.com / filogic / uboot / 71a9d1a387bf50e55426cdd86a6749d52101bb7a / . / arch / powerpc / include / asm / fsl_secure_boot.h
blob: 221f9d842a8326984e705a6303c95eff68e1982d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000[diff] [blame]2/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000[diff] [blame]4 */
5
6#ifndef __FSL_SECURE_BOOT_H
7#define __FSL_SECURE_BOOT_H
gaurav rana8b5ea652015-02-27 09:46:17 +0530[diff] [blame]8#include <asm/config_mpc85xx.h>
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000[diff] [blame]9
Udit Agarwald2dd2f72019-11-07 16:11:39 +0000[diff] [blame]10#ifdef CONFIG_NXP_ESBC
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000[diff] [blame]11#if defined(CONFIG_FSL_CORENET)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]12#define CFG_SYS_PBI_FLASH_BASE 0xc0000000
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000[diff] [blame]13#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]14#define CFG_SYS_PBI_FLASH_BASE 0xce000000
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000[diff] [blame]15#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]16#define CFG_SYS_PBI_FLASH_WINDOW 0xcff80000
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000[diff] [blame]17
Tom Rinibf1dfd82022-06-17 16:24:34 -0400[diff] [blame]18#if defined(CONFIG_TARGET_T2080QDS) || \
York Suna05baa42016-12-28 08:43:37 -0800[diff] [blame]19 defined(CONFIG_TARGET_T2080RDB) || \
York Sun097aa602016-11-21 11:25:26 -0800[diff] [blame]20 defined(CONFIG_TARGET_T1042D4RDB) || \
York Sun7d29dd62016-11-18 13:01:34 -0800[diff] [blame]21 defined(CONFIG_ARCH_T1024)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]22#undef CFG_SYS_INIT_L3_ADDR
23#define CFG_SYS_INIT_L3_ADDR 0xbff00000
Aneesh Bansal8bcbc272014-03-18 23:40:26 +0530[diff] [blame]24#endif
25
Aneesh Bansale0f50152015-06-16 10:36:00 +0530[diff] [blame]26#if defined(CONFIG_RAMBOOT_PBL)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]27#undef CFG_SYS_INIT_L3_ADDR
28#ifdef CFG_SYS_INIT_L3_VADDR
29#define CFG_SYS_INIT_L3_ADDR \
30 (CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
Sumit Gargafaca2a2016-07-14 12:27:52 -0400[diff] [blame]31 0xbff00000
32#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]33#define CFG_SYS_INIT_L3_ADDR 0xbff00000
Sumit Gargafaca2a2016-07-14 12:27:52 -0400[diff] [blame]34#endif
Aneesh Bansale0f50152015-06-16 10:36:00 +0530[diff] [blame]35#endif
Udit Agarwald2dd2f72019-11-07 16:11:39 +0000[diff] [blame]36#endif /* #ifdef CONFIG_NXP_ESBC */
gaurav rana8b5ea652015-02-27 09:46:17 +0530[diff] [blame]37
Aneesh Bansal43104702016-01-22 16:37:24 +0530[diff] [blame]38#ifdef CONFIG_CHAIN_OF_TRUST
Simon Glass3aa66122016-09-12 23:18:23 -0600[diff] [blame]39#ifdef CONFIG_SPL_BUILD
Sumit Gargf6d96cb2016-07-14 12:27:51 -0400[diff] [blame]40/*
41 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
42 * due to space crunch on CPC and thus malloc will not work.
43 */
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]44#define CFG_SPL_PPAACT_ADDR 0x2e000000
45#define CFG_SPL_SPAACT_ADDR 0x2f000000
46#define CFG_SPL_JR0_LIODN_S 454
47#define CFG_SPL_JR0_LIODN_NS 458
Sumit Gargf6d96cb2016-07-14 12:27:51 -0400[diff] [blame]48#endif /* ifdef CONFIG_SPL_BUILD */
49
Sumit Gargf6d96cb2016-07-14 12:27:51 -0400[diff] [blame]50#ifndef CONFIG_SPL_BUILD
Aneesh Bansal43104702016-01-22 16:37:24 +0530[diff] [blame]51#include <config_fsl_chain_trust.h>
Sumit Gargf6d96cb2016-07-14 12:27:51 -0400[diff] [blame]52#endif /* #ifndef CONFIG_SPL_BUILD */
Aneesh Bansal43104702016-01-22 16:37:24 +0530[diff] [blame]53#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
Po Liud1030092013-08-21 14:20:21 +0800[diff] [blame]54#endif