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git01.mediatek.com / filogic / uboot / 705d5d7b7be63eea1bc0b1177b5db58e19a2826e / . / configs / firefly-rk3288_defconfig
blob: 3b605f4ba49b9a3ae4be6023635fefbb17047ba1 [file] [log] [blame]
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
Jacob Chen503b8572017-01-17 12:19:39 +0800[diff] [blame]5CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]6CONFIG_TARGET_FIREFLY_RK3288=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]7CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]9CONFIG_DEBUG_UART=y
Simon Glass73c18b42017-07-23 21:19:39 -0600[diff] [blame]10CONFIG_ENV_IS_IN_MMC=y
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]11CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]12# CONFIG_DISPLAY_CPUINFO is not set
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]13CONFIG_SPL_STACK_R=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]14CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]15# CONFIG_CMD_IMLS is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]16CONFIG_CMD_GPT=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]17CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]18CONFIG_CMD_SF=y
19CONFIG_CMD_SPI=y
20CONFIG_CMD_I2C=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]21CONFIG_CMD_USB=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]22CONFIG_CMD_GPIO=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]23# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]24CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]25CONFIG_CMD_TIME=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]26CONFIG_CMD_PMIC=y
27CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]28# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]29# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]30# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]31CONFIG_SPL_PARTITION_UUIDS=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]32CONFIG_SPL_OF_CONTROL=y
Simon Glass813d4602016-05-14 14:03:00 -0600[diff] [blame]33CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Romain Perier04cad6e2017-01-17 10:32:25 +0100[diff] [blame]34CONFIG_NET_RANDOM_ETHADDR=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]35CONFIG_REGMAP=y
huang lindd8515e2015-11-17 14:20:13 +0800[diff] [blame]36CONFIG_SPL_REGMAP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]37CONFIG_SYSCON=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]38CONFIG_SPL_SYSCON=y
Simon Glass70bad912016-01-21 19:43:49 -0700[diff] [blame]39# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]40CONFIG_CLK=y
41CONFIG_SPL_CLK=y
42CONFIG_ROCKCHIP_GPIO=y
43CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]44CONFIG_LED=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]45CONFIG_LED_GPIO=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]46CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]47CONFIG_MMC_DW_ROCKCHIP=y
Sjoerd Simons613848c2017-01-11 11:46:12 +0100[diff] [blame]48CONFIG_DM_ETH=y
Sjoerd Simons613848c2017-01-11 11:46:12 +0100[diff] [blame]49CONFIG_ETH_DESIGNWARE=y
50CONFIG_GMAC_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]51CONFIG_PINCTRL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]52CONFIG_SPL_PINCTRL=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]53# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]54CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]55CONFIG_DM_PMIC=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]56# CONFIG_SPL_PMIC_CHILDREN is not set
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]57CONFIG_PMIC_ACT8846=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]58CONFIG_REGULATOR_ACT8846=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]59CONFIG_DM_REGULATOR_FIXED=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]60CONFIG_PWM_ROCKCHIP=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]61CONFIG_RAM=y
62CONFIG_SPL_RAM=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]63CONFIG_DEBUG_UART_BASE=0xff690000
64CONFIG_DEBUG_UART_CLOCK=24000000
65CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]66CONFIG_SYS_NS16550=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]67CONFIG_SYSRESET=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]68CONFIG_USB=y
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]69CONFIG_USB_DWC2=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]70CONFIG_USB_STORAGE=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]71CONFIG_DM_VIDEO=y
Anatolij Gustschin4601eb42016-01-25 17:17:22 +0100[diff] [blame]72CONFIG_DISPLAY=y
Simon Glass52de6462016-01-21 19:45:20 -0700[diff] [blame]73CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]74CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glassd76f29a2016-10-17 20:12:57 -0600[diff] [blame]75CONFIG_CONSOLE_SCROLL_LINES=10
Sjoerd Simonsf26619a2015-12-04 23:27:41 +0100[diff] [blame]76CONFIG_USE_TINY_PRINTF=y
Simon Glassec3be542015-08-30 16:55:41 -0600[diff] [blame]77CONFIG_CMD_DHRYSTONE=y
78CONFIG_ERRNO_STR=y