| Simon Glass | fcc2ce9 | 2019-12-08 17:40:17 -0700 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | # |
| 3 | # Copyright 2019 Google LLC |
| 4 | # |
| 5 | |
| 6 | config INTEL_APOLLOLAKE |
| 7 | bool |
| 8 | select FSP_VERSION2 |
| 9 | select HAVE_FSP |
| 10 | select ARCH_MISC_INIT |
| 11 | select USE_CAR |
| 12 | select INTEL_PMC |
| 13 | select TPL_X86_TSC_TIMER_NATIVE |
| 14 | select SPL_PCH_SUPPORT |
| 15 | select TPL_PCH_SUPPORT |
| Simon Glass | 741ce46 | 2020-09-22 12:44:51 -0600 | [diff] [blame] | 16 | select PCIEX_LENGTH_256MB |
| Simon Glass | fcc2ce9 | 2019-12-08 17:40:17 -0700 | [diff] [blame] | 17 | select PCH_SUPPORT |
| 18 | select P2SB |
| Simon Glass | 4a30bbb | 2020-07-17 08:48:16 -0600 | [diff] [blame] | 19 | select SMP_AP_WORK |
| Simon Glass | fcc2ce9 | 2019-12-08 17:40:17 -0700 | [diff] [blame] | 20 | imply ENABLE_MRC_CACHE |
| 21 | imply AHCI_PCI |
| 22 | imply SCSI |
| 23 | imply SCSI_AHCI |
| 24 | imply SPI_FLASH |
| 25 | imply USB |
| 26 | imply USB_EHCI_HCD |
| 27 | imply TPL |
| 28 | imply SPL |
| 29 | imply TPL_X86_16BIT_INIT |
| 30 | imply TPL_OF_PLATDATA |
| 31 | imply ACPI_PMC |
| 32 | imply MMC |
| 33 | imply DM_MMC |
| 34 | imply MMC_PCI |
| 35 | imply MMC_SDHCI |
| 36 | imply CMD_MMC |
| 37 | imply VIDEO_FSP |
| 38 | imply PINCTRL_INTEL |
| 39 | imply PINCTRL_INTEL_APL |
| 40 | imply HAVE_VBT |
| 41 | imply HAVE_X86_FIT |
| 42 | imply INTEL_GPIO |
| 43 | imply SMP |
| Wolfgang Wallner | b5460dd | 2020-02-03 14:06:45 +0100 | [diff] [blame] | 44 | imply HAVE_ITSS |
| Wolfgang Wallner | 21fae58 | 2020-02-04 09:04:56 +0100 | [diff] [blame] | 45 | imply HAVE_P2SB |
| Simon Glass | 4a2c26a | 2020-02-06 09:54:54 -0700 | [diff] [blame] | 46 | imply CLK |
| 47 | imply CMD_CLK |
| 48 | imply CLK_INTEL |
| Simon Glass | c061974 | 2020-02-06 09:55:02 -0700 | [diff] [blame] | 49 | imply ACPI_GPE |
| Simon Glass | fcc2ce9 | 2019-12-08 17:40:17 -0700 | [diff] [blame] | 50 | |
| 51 | if INTEL_APOLLOLAKE |
| 52 | |
| 53 | config DCACHE_RAM_BASE |
| 54 | default 0xfef00000 |
| 55 | |
| 56 | config DCACHE_RAM_SIZE |
| 57 | default 0xc0000 |
| 58 | |
| 59 | config DCACHE_RAM_MRC_VAR_SIZE |
| 60 | default 0xb0000 |
| 61 | |
| 62 | config CPU_SPECIFIC_OPTIONS |
| 63 | def_bool y |
| 64 | select SMM_TSEG |
| 65 | select X86_RAMTEST |
| 66 | |
| 67 | config SMM_TSEG_SIZE |
| 68 | hex |
| 69 | default 0x800000 |
| 70 | |
| 71 | config MMCONF_BASE_ADDRESS |
| 72 | hex |
| 73 | default 0xe0000000 |
| 74 | |
| 75 | config TPL_SIZE_LIMIT |
| 76 | default 0x7800 |
| 77 | |
| 78 | config CPU_ADDR_BITS |
| 79 | default 39 |
| 80 | |
| 81 | config APL_SPI_FLASH_BOOT |
| 82 | bool "Support booting with SPI-flash driver instead memory-mapped SPI" |
| 83 | select TPL_SPI_FLASH_SUPPORT |
| 84 | select TPL_SPI_SUPPORT |
| 85 | help |
| 86 | This enables SPI and SPI flash in TPL. Without the this only |
| 87 | available boot method is to use memory-mapped SPI. Since this is |
| 88 | actually fast and produces a TPL which is 7KB smaller, memory-mapped |
| 89 | SPI is the default. |
| 90 | |
| 91 | config APL_BOOT_FROM_FAST_SPI_FLASH |
| 92 | bool "Boot using SPI flash driver" |
| 93 | select APL_SPI_FLASH_BOOT |
| 94 | help |
| 95 | This option is separate from APL_SPI_FLASH_BOOT since it is useful to |
| 96 | be able to compare booting speed with the same build. Enable this to |
| 97 | use the SPI-flash driver to load SPL, U-Boot and FSP-M. For technical |
| 98 | reasons FSP-S is currently always loaded from memory-mapped SPI. See |
| 99 | Apollo Lake's arch_fsp_init_r() for details about that. |
| 100 | |
| 101 | config VBT_ADDR |
| 102 | default 0xff3f1000 |
| 103 | |
| 104 | endif |