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git01.mediatek.com / filogic / uboot / 6fd4e0bab5e1b67b5e4c4230c8180a7e7ac41eed / . / arch / arm / mach-socfpga / Kconfig
blob: 1d914648e314fbfde805c3947c2a1d927b3fb486 [file] [log] [blame]
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]3config NR_DRAM_BANKS
4 default 1
5
Simon Goldschmidt20fd7de2019-06-13 21:50:28 +0200[diff] [blame]6config SPL_SIZE_LIMIT
7 default 65536 if TARGET_SOCFPGA_GEN5
8
9config SPL_SIZE_LIMIT_PROVIDE_STACK
10 default 0x200 if TARGET_SOCFPGA_GEN5
11
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]12config SPL_STACK_R_ADDR
13 default 0x00800000 if TARGET_SOCFPGA_GEN5
14
Simon Goldschmidt4f57b9a2019-04-09 21:02:06 +0200[diff] [blame]15config SPL_SYS_MALLOC_F_LEN
16 default 0x800 if TARGET_SOCFPGA_GEN5
17
Dalon Westergreen8d770f42017-02-10 17:15:34 -0800[diff] [blame]18config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
19 default 0xa2
20
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]21config SYS_MALLOC_F_LEN
22 default 0x2000 if TARGET_SOCFPGA_ARRIA10
23 default 0x2000 if TARGET_SOCFPGA_GEN5
24
25config SYS_TEXT_BASE
26 default 0x01000040 if TARGET_SOCFPGA_ARRIA10
27 default 0x01000040 if TARGET_SOCFPGA_GEN5
28
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]29config TARGET_SOCFPGA_ARRIA5
30 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]31 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]32
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]33config TARGET_SOCFPGA_ARRIA10
34 bool
Ley Foon Tan17b9ba62019-05-06 09:55:59 +0800[diff] [blame]35 select SPL_ALTERA_SDRAM
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]36 select SPL_BOARD_INIT if SPL
Marek Vasute1dcd622018-07-30 15:56:19 +0200[diff] [blame]37 select CLK
38 select SPL_CLK if SPL
Marek Vasut69fbb882018-08-13 18:32:38 +0200[diff] [blame]39 select DM_I2C
Marek Vasut700b2c62018-08-13 18:32:38 +0200[diff] [blame]40 select DM_RESET
41 select SPL_DM_RESET if SPL
Marek Vasut04c8f4f2018-08-13 20:06:46 +0200[diff] [blame]42 select REGMAP
43 select SPL_REGMAP if SPL
44 select SYSCON
45 select SPL_SYSCON if SPL
46 select ETH_DESIGNWARE_SOCFPGA
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]47 imply FPGA_SOCFPGA
48 imply USE_TINY_PRINTF
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]49
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]50config TARGET_SOCFPGA_CYCLONE5
51 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]52 select TARGET_SOCFPGA_GEN5
53
54config TARGET_SOCFPGA_GEN5
55 bool
Ley Foon Tan17b9ba62019-05-06 09:55:59 +0800[diff] [blame]56 select SPL_ALTERA_SDRAM
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]57 imply FPGA_SOCFPGA
Simon Goldschmidt20fd7de2019-06-13 21:50:28 +0200[diff] [blame]58 imply SPL_SIZE_LIMIT_SUBTRACT_GD
59 imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]60 imply SPL_STACK_R
61 imply SPL_SYS_MALLOC_SIMPLE
62 imply USE_TINY_PRINTF
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]63
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]64config TARGET_SOCFPGA_STRATIX10
65 bool
66 select ARMV8_MULTIENTRY
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]67 select ARMV8_SET_SMPEN
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]68 select ARMV8_SPIN_TABLE
Ang, Chee Hongda9640e2018-12-19 18:35:16 -0800[diff] [blame]69 select FPGA_STRATIX10
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]70
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]71choice
72 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]73 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]74
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200[diff] [blame]75config TARGET_SOCFPGA_ARIES_MCVEVK
76 bool "Aries MCVEVK (Cyclone V)"
77 select TARGET_SOCFPGA_CYCLONE5
78
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]79config TARGET_SOCFPGA_ARRIA10_SOCDK
80 bool "Altera SOCFPGA SoCDK (Arria 10)"
81 select TARGET_SOCFPGA_ARRIA10
82
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]83config TARGET_SOCFPGA_ARRIA5_SOCDK
84 bool "Altera SOCFPGA SoCDK (Arria V)"
85 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]86
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]87config TARGET_SOCFPGA_CYCLONE5_SOCDK
88 bool "Altera SOCFPGA SoCDK (Cyclone V)"
89 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]90
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]91config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
92 bool "Devboards DBM-SoC1 (Cyclone V)"
93 select TARGET_SOCFPGA_CYCLONE5
94
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]95config TARGET_SOCFPGA_EBV_SOCRATES
96 bool "EBV SoCrates (Cyclone V)"
97 select TARGET_SOCFPGA_CYCLONE5
98
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]99config TARGET_SOCFPGA_IS1
100 bool "IS1 (Cyclone V)"
101 select TARGET_SOCFPGA_CYCLONE5
102
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]103config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
104 bool "samtec VIN|ING FPGA (Cyclone V)"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]105 select BOARD_LATE_INIT
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]106 select TARGET_SOCFPGA_CYCLONE5
107
Marek Vasut2e717ec2016-06-08 02:57:05 +0200[diff] [blame]108config TARGET_SOCFPGA_SR1500
109 bool "SR1500 (Cyclone V)"
110 select TARGET_SOCFPGA_CYCLONE5
111
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]112config TARGET_SOCFPGA_STRATIX10_SOCDK
113 bool "Intel SOCFPGA SoCDK (Stratix 10)"
114 select TARGET_SOCFPGA_STRATIX10
115
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]116config TARGET_SOCFPGA_TERASIC_DE0_NANO
117 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
118 select TARGET_SOCFPGA_CYCLONE5
119
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]120config TARGET_SOCFPGA_TERASIC_DE10_NANO
121 bool "Terasic DE10-Nano (Cyclone V)"
122 select TARGET_SOCFPGA_CYCLONE5
123
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]124config TARGET_SOCFPGA_TERASIC_DE1_SOC
125 bool "Terasic DE1-SoC (Cyclone V)"
126 select TARGET_SOCFPGA_CYCLONE5
127
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]128config TARGET_SOCFPGA_TERASIC_SOCKIT
129 bool "Terasic SoCkit (Cyclone V)"
130 select TARGET_SOCFPGA_CYCLONE5
131
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]132endchoice
133
134config SYS_BOARD
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]135 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]136 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]137 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]138 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]139 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]140 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]141 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]142 default "is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200[diff] [blame]143 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]144 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]145 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]146 default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]147 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]148 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]149
150config SYS_VENDOR
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]151 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]152 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]153 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]154 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200[diff] [blame]155 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]156 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]157 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]158 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]159 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]160 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]161 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]162 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]163
164config SYS_SOC
165 default "socfpga"
166
167config SYS_CONFIG_NAME
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]168 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]169 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]170 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]171 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]172 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]173 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]174 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]175 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200[diff] [blame]176 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]177 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]178 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]179 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]180 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]181 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]182
183endif