wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 2 | * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 3 | * (C) Copyright 2002, 2003 Motorola Inc. |
| 4 | * Xianghua Xiao (X.Xiao@motorola.com) |
| 5 | * |
| 6 | * (C) Copyright 2000 |
| 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
Andy Fleming | fecff2b | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 28 | #include <config.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 29 | #include <common.h> |
| 30 | #include <watchdog.h> |
| 31 | #include <command.h> |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 32 | #include <fsl_esdhc.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 33 | #include <asm/cache.h> |
Sergei Poselenov | ddc1a47 | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 34 | #include <asm/io.h> |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 35 | #include <asm/mmu.h> |
Dipen Dudhat | 00c4294 | 2011-01-20 16:29:35 +0530 | [diff] [blame] | 36 | #include <asm/fsl_ifc.h> |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 37 | #include <asm/fsl_law.h> |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 38 | #include <asm/fsl_lbc.h> |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 39 | #include <post.h> |
| 40 | #include <asm/processor.h> |
| 41 | #include <asm/fsl_ddr_sdram.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 42 | |
James Yang | 957b191 | 2008-02-08 16:44:53 -0600 | [diff] [blame] | 43 | DECLARE_GLOBAL_DATA_PTR; |
| 44 | |
Ira W. Snyder | a85994c | 2011-11-21 13:20:32 -0800 | [diff] [blame] | 45 | /* |
| 46 | * Default board reset function |
| 47 | */ |
| 48 | static void |
| 49 | __board_reset(void) |
| 50 | { |
| 51 | /* Do nothing */ |
| 52 | } |
| 53 | void board_reset(void) __attribute__((weak, alias("__board_reset"))); |
| 54 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 55 | int checkcpu (void) |
| 56 | { |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 57 | sys_info_t sysinfo; |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 58 | uint pvr, svr; |
| 59 | uint ver; |
| 60 | uint major, minor; |
Kumar Gala | 8ddf00c | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 61 | struct cpu_type *cpu; |
Wolfgang Denk | 2059104 | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 62 | char buf1[32], buf2[32]; |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 63 | #if (defined(CONFIG_DDR_CLK_FREQ) || \ |
| 64 | defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Kumar Gala | 1d39c9a | 2010-04-13 11:07:57 -0500 | [diff] [blame] | 66 | #endif /* CONFIG_FSL_CORENET */ |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Cornet platforms use ddr sync bit in RCW to indicate sync vs async |
| 70 | * mode. Previous platform use ddr ratio to do the same. This |
| 71 | * information is only for display here. |
| 72 | */ |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 73 | #ifdef CONFIG_FSL_CORENET |
York Sun | 383f6f6 | 2012-10-08 07:44:16 +0000 | [diff] [blame] | 74 | #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 75 | u32 ddr_sync = 0; /* only async mode is supported */ |
York Sun | 383f6f6 | 2012-10-08 07:44:16 +0000 | [diff] [blame] | 76 | #else |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 77 | u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) |
Srikanth Srinivasan | f58c2a4 | 2010-02-10 17:32:43 +0800 | [diff] [blame] | 78 | >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; |
York Sun | 383f6f6 | 2012-10-08 07:44:16 +0000 | [diff] [blame] | 79 | #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 80 | #else /* CONFIG_FSL_CORENET */ |
| 81 | #ifdef CONFIG_DDR_CLK_FREQ |
| 82 | u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) |
| 83 | >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; |
Kumar Gala | 54b6810 | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 84 | #else |
| 85 | u32 ddr_ratio = 0; |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 86 | #endif /* CONFIG_DDR_CLK_FREQ */ |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 87 | #endif /* CONFIG_FSL_CORENET */ |
| 88 | |
Timur Tabi | 4728942 | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 89 | unsigned int i, core, nr_cores = cpu_numcores(); |
| 90 | u32 mask = cpu_mask(); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 91 | |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 92 | svr = get_svr(); |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 93 | major = SVR_MAJ(svr); |
| 94 | minor = SVR_MIN(svr); |
| 95 | |
Poonam Aggrwal | 4baef82 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 96 | if (cpu_numcores() > 1) { |
Poonam Aggrwal | 36a6843 | 2009-09-03 19:42:40 +0530 | [diff] [blame] | 97 | #ifndef CONFIG_MP |
| 98 | puts("Unicore software on multiprocessor system!!\n" |
| 99 | "To enable mutlticore build define CONFIG_MP\n"); |
| 100 | #endif |
Kim Phillips | 2ecbfeb | 2010-08-09 18:39:57 -0500 | [diff] [blame] | 101 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); |
Poonam Aggrwal | 4baef82 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 102 | printf("CPU%d: ", pic->whoami); |
| 103 | } else { |
| 104 | puts("CPU: "); |
| 105 | } |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 106 | |
Simon Glass | a8b5739 | 2012-12-13 20:48:48 +0000 | [diff] [blame] | 107 | cpu = gd->arch.cpu; |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 108 | |
Poonam Aggrwal | da6e1ca | 2009-09-02 13:35:21 +0530 | [diff] [blame] | 109 | puts(cpu->name); |
| 110 | if (IS_E_PROCESSOR(svr)) |
| 111 | puts("E"); |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 112 | |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 113 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 114 | |
wdenk | 3f3262b | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 115 | pvr = get_pvr(); |
| 116 | ver = PVR_VER(pvr); |
| 117 | major = PVR_MAJ(pvr); |
| 118 | minor = PVR_MIN(pvr); |
| 119 | |
| 120 | printf("Core: "); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 121 | switch(ver) { |
| 122 | case PVR_VER_E500_V1: |
| 123 | case PVR_VER_E500_V2: |
Fabio Estevam | f4c557c | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 124 | puts("e500"); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 125 | break; |
| 126 | case PVR_VER_E500MC: |
Fabio Estevam | f4c557c | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 127 | puts("e500mc"); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 128 | break; |
| 129 | case PVR_VER_E5500: |
Fabio Estevam | f4c557c | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 130 | puts("e5500"); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 131 | break; |
Kumar Gala | c1abf4a | 2012-08-17 08:20:23 +0000 | [diff] [blame] | 132 | case PVR_VER_E6500: |
Fabio Estevam | f4c557c | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 133 | puts("e6500"); |
Kumar Gala | c1abf4a | 2012-08-17 08:20:23 +0000 | [diff] [blame] | 134 | break; |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 135 | default: |
Kumar Gala | bd2985c | 2009-10-21 13:23:54 -0500 | [diff] [blame] | 136 | puts("Unknown"); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 137 | break; |
wdenk | 3f3262b | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 138 | } |
Kumar Gala | 9f4a689 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 139 | |
wdenk | 3f3262b | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 140 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
| 141 | |
York Sun | 908412d | 2012-10-08 07:44:10 +0000 | [diff] [blame] | 142 | if (nr_cores > CONFIG_MAX_CPUS) { |
| 143 | panic("\nUnexpected number of cores: %d, max is %d\n", |
| 144 | nr_cores, CONFIG_MAX_CPUS); |
| 145 | } |
| 146 | |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 147 | get_sys_info(&sysinfo); |
| 148 | |
Kumar Gala | f92794c | 2009-02-04 09:35:57 -0600 | [diff] [blame] | 149 | puts("Clock Configuration:"); |
Timur Tabi | 4728942 | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 150 | for_each_cpu(i, core, nr_cores, mask) { |
Wolfgang Denk | 1f79d14 | 2009-02-19 00:41:08 +0100 | [diff] [blame] | 151 | if (!(i & 3)) |
| 152 | printf ("\n "); |
Timur Tabi | 4728942 | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 153 | printf("CPU%d:%-4s MHz, ", core, |
| 154 | strmhz(buf1, sysinfo.freqProcessor[core])); |
Kumar Gala | f92794c | 2009-02-04 09:35:57 -0600 | [diff] [blame] | 155 | } |
| 156 | printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); |
Kumar Gala | 54b6810 | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 157 | |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 158 | #ifdef CONFIG_FSL_CORENET |
| 159 | if (ddr_sync == 1) { |
| 160 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 161 | "(Synchronous), ", |
| 162 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 163 | strmhz(buf2, sysinfo.freqDDRBus)); |
| 164 | } else { |
| 165 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 166 | "(Asynchronous), ", |
| 167 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 168 | strmhz(buf2, sysinfo.freqDDRBus)); |
| 169 | } |
| 170 | #else |
Kumar Gala | 07db170 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 171 | switch (ddr_ratio) { |
| 172 | case 0x0: |
Wolfgang Denk | 2059104 | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 173 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", |
| 174 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 175 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | 07db170 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 176 | break; |
| 177 | case 0x7: |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 178 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 179 | "(Synchronous), ", |
Wolfgang Denk | 2059104 | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 180 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 181 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | 07db170 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 182 | break; |
| 183 | default: |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 184 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 185 | "(Asynchronous), ", |
Wolfgang Denk | 2059104 | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 186 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 187 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | 07db170 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 188 | break; |
| 189 | } |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 190 | #endif |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 191 | |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 192 | #if defined(CONFIG_FSL_LBC) |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 193 | if (sysinfo.freqLocalBus > LCRR_CLKDIV) { |
Trent Piepho | 0b691fc | 2008-12-03 15:16:37 -0800 | [diff] [blame] | 194 | printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 195 | } else { |
Trent Piepho | 0b691fc | 2008-12-03 15:16:37 -0800 | [diff] [blame] | 196 | printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", |
| 197 | sysinfo.freqLocalBus); |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 198 | } |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 199 | #endif |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 200 | |
Kumar Gala | 17ec6fa | 2012-10-08 07:44:06 +0000 | [diff] [blame] | 201 | #if defined(CONFIG_FSL_IFC) |
| 202 | printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); |
| 203 | #endif |
| 204 | |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 205 | #ifdef CONFIG_CPM2 |
Wolfgang Denk | 2059104 | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 206 | printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 207 | #endif |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 208 | |
Haiying Wang | 6141468 | 2009-05-20 12:30:29 -0400 | [diff] [blame] | 209 | #ifdef CONFIG_QE |
| 210 | printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); |
| 211 | #endif |
| 212 | |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 213 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 214 | for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { |
Emil Medve | 3a9ed2f | 2010-06-17 00:08:29 -0500 | [diff] [blame] | 215 | printf(" FMAN%d: %s MHz\n", i + 1, |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 216 | strmhz(buf1, sysinfo.freqFMan[i])); |
| 217 | } |
| 218 | #endif |
| 219 | |
Haiying Wang | 09d0aa9 | 2012-10-11 07:13:39 +0000 | [diff] [blame] | 220 | #ifdef CONFIG_SYS_DPAA_QBMAN |
| 221 | printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); |
| 222 | #endif |
| 223 | |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 224 | #ifdef CONFIG_SYS_DPAA_PME |
| 225 | printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); |
| 226 | #endif |
| 227 | |
wdenk | 3f3262b | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 228 | puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | |
| 234 | /* ------------------------------------------------------------------------- */ |
| 235 | |
Mike Frysinger | 6d1f698 | 2010-10-20 03:41:17 -0400 | [diff] [blame] | 236 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 237 | { |
Kumar Gala | aff0153 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 238 | /* Everything after the first generation of PQ3 parts has RSTCR */ |
| 239 | #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ |
| 240 | defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) |
Sergei Poselenov | 2514742 | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 241 | unsigned long val, msr; |
| 242 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 243 | /* |
| 244 | * Initiate hard reset in debug control register DBCR0 |
Kumar Gala | aff0153 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 245 | * Make sure MSR[DE] = 1. This only resets the core. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 246 | */ |
Sergei Poselenov | 2514742 | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 247 | msr = mfmsr (); |
| 248 | msr |= MSR_DE; |
| 249 | mtmsr (msr); |
urwithsughosh@gmail.com | 06c2fb9 | 2007-09-24 13:32:13 -0400 | [diff] [blame] | 250 | |
Sergei Poselenov | 2514742 | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 251 | val = mfspr(DBCR0); |
| 252 | val |= 0x70000000; |
| 253 | mtspr(DBCR0,val); |
Kumar Gala | aff0153 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 254 | #else |
| 255 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Ira W. Snyder | a85994c | 2011-11-21 13:20:32 -0800 | [diff] [blame] | 256 | |
| 257 | /* Attempt board-specific reset */ |
| 258 | board_reset(); |
| 259 | |
| 260 | /* Next try asserting HRESET_REQ */ |
| 261 | out_be32(&gur->rstcr, 0x2); |
Kumar Gala | aff0153 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 262 | udelay(100); |
| 263 | #endif |
Sergei Poselenov | 2514742 | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 264 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 265 | return 1; |
| 266 | } |
| 267 | |
| 268 | |
| 269 | /* |
| 270 | * Get timebase clock frequency |
| 271 | */ |
Kumar Gala | f4fb90f | 2011-02-18 05:40:54 -0600 | [diff] [blame] | 272 | #ifndef CONFIG_SYS_FSL_TBCLK_DIV |
| 273 | #define CONFIG_SYS_FSL_TBCLK_DIV 8 |
| 274 | #endif |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 275 | unsigned long get_tbclk (void) |
| 276 | { |
Kumar Gala | f4fb90f | 2011-02-18 05:40:54 -0600 | [diff] [blame] | 277 | unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; |
| 278 | |
| 279 | return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | |
| 283 | #if defined(CONFIG_WATCHDOG) |
| 284 | void |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 285 | reset_85xx_watchdog(void) |
| 286 | { |
| 287 | /* |
| 288 | * Clear TSR(WIS) bit by writing 1 |
| 289 | */ |
Mark Marshall | 10b13c9 | 2012-09-09 23:06:03 +0000 | [diff] [blame] | 290 | mtspr(SPRN_TSR, TSR_WIS); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 291 | } |
Horst Kronstorfer | f70831e | 2013-03-13 10:14:05 +0000 | [diff] [blame] | 292 | |
| 293 | void |
| 294 | watchdog_reset(void) |
| 295 | { |
| 296 | int re_enable = disable_interrupts(); |
| 297 | |
| 298 | reset_85xx_watchdog(); |
| 299 | if (re_enable) |
| 300 | enable_interrupts(); |
| 301 | } |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 302 | #endif /* CONFIG_WATCHDOG */ |
| 303 | |
Sergei Poselenov | ddc1a47 | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 304 | /* |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 305 | * Initializes on-chip MMC controllers. |
| 306 | * to override, implement board_mmc_init() |
| 307 | */ |
| 308 | int cpu_mmc_init(bd_t *bis) |
| 309 | { |
| 310 | #ifdef CONFIG_FSL_ESDHC |
| 311 | return fsl_esdhc_mmc_init(bis); |
| 312 | #else |
| 313 | return 0; |
| 314 | #endif |
| 315 | } |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 316 | |
| 317 | /* |
| 318 | * Print out the state of various machine registers. |
Dipen Dudhat | 00c4294 | 2011-01-20 16:29:35 +0530 | [diff] [blame] | 319 | * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing |
| 320 | * parameters for IFC and TLBs |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 321 | */ |
| 322 | void mpc85xx_reginfo(void) |
| 323 | { |
| 324 | print_tlbcam(); |
| 325 | print_laws(); |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 326 | #if defined(CONFIG_FSL_LBC) |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 327 | print_lbc_regs(); |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 328 | #endif |
Dipen Dudhat | 00c4294 | 2011-01-20 16:29:35 +0530 | [diff] [blame] | 329 | #ifdef CONFIG_FSL_IFC |
| 330 | print_ifc_regs(); |
| 331 | #endif |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 332 | |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 333 | } |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 334 | |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 335 | /* Common ddr init for non-corenet fsl 85xx platforms */ |
| 336 | #ifndef CONFIG_FSL_CORENET |
Scott Wood | 095b712 | 2012-09-20 19:02:18 -0500 | [diff] [blame] | 337 | #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ |
| 338 | !defined(CONFIG_SYS_INIT_L2_ADDR) |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 339 | phys_size_t initdram(int board_type) |
| 340 | { |
Zhao Chenhui | 1a35f3d | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 341 | #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) |
| 342 | return fsl_ddr_sdram_size(); |
| 343 | #else |
Mingkai Hu | abe3a3f | 2013-04-12 15:56:28 +0800 | [diff] [blame] | 344 | return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
Zhao Chenhui | 1a35f3d | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 345 | #endif |
| 346 | } |
| 347 | #else /* CONFIG_SYS_RAMBOOT */ |
| 348 | phys_size_t initdram(int board_type) |
| 349 | { |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 350 | phys_size_t dram_size = 0; |
| 351 | |
Becky Bruce | 4212f23 | 2010-12-17 17:17:58 -0600 | [diff] [blame] | 352 | #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 353 | { |
| 354 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 355 | unsigned int x = 10; |
| 356 | unsigned int i; |
| 357 | |
| 358 | /* |
| 359 | * Work around to stabilize DDR DLL |
| 360 | */ |
| 361 | out_be32(&gur->ddrdllcr, 0x81000000); |
| 362 | asm("sync;isync;msync"); |
| 363 | udelay(200); |
| 364 | while (in_be32(&gur->ddrdllcr) != 0x81000100) { |
| 365 | setbits_be32(&gur->devdisr, 0x00010000); |
| 366 | for (i = 0; i < x; i++) |
| 367 | ; |
| 368 | clrbits_be32(&gur->devdisr, 0x00010000); |
| 369 | x++; |
| 370 | } |
| 371 | } |
| 372 | #endif |
| 373 | |
York Sun | e73cc04 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 374 | #if defined(CONFIG_SPD_EEPROM) || \ |
| 375 | defined(CONFIG_DDR_SPD) || \ |
| 376 | defined(CONFIG_SYS_DDR_RAW_TIMING) |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 377 | dram_size = fsl_ddr_sdram(); |
| 378 | #else |
| 379 | dram_size = fixed_sdram(); |
| 380 | #endif |
| 381 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
| 382 | dram_size *= 0x100000; |
| 383 | |
| 384 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 385 | /* |
| 386 | * Initialize and enable DDR ECC. |
| 387 | */ |
| 388 | ddr_enable_ecc(dram_size); |
| 389 | #endif |
| 390 | |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 391 | #if defined(CONFIG_FSL_LBC) |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 392 | /* Some boards also have sdram on the lbc */ |
Becky Bruce | b88d3d0 | 2010-12-17 17:17:57 -0600 | [diff] [blame] | 393 | lbc_sdram_init(); |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 394 | #endif |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 395 | |
Wolfgang Denk | f2bbb53 | 2011-07-25 10:13:53 +0200 | [diff] [blame] | 396 | debug("DDR: "); |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 397 | return dram_size; |
| 398 | } |
Zhao Chenhui | 1a35f3d | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 399 | #endif /* CONFIG_SYS_RAMBOOT */ |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 400 | #endif |
| 401 | |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 402 | #if CONFIG_POST & CONFIG_SYS_POST_MEMORY |
| 403 | |
| 404 | /* Board-specific functions defined in each board's ddr.c */ |
| 405 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
| 406 | unsigned int ctrl_num); |
| 407 | void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, |
| 408 | phys_addr_t *rpn); |
| 409 | unsigned int |
| 410 | setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); |
| 411 | |
Becky Bruce | 6969447 | 2011-07-18 18:49:15 -0500 | [diff] [blame] | 412 | void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); |
| 413 | |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 414 | static void dump_spd_ddr_reg(void) |
| 415 | { |
| 416 | int i, j, k, m; |
| 417 | u8 *p_8; |
| 418 | u32 *p_32; |
| 419 | ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; |
| 420 | generic_spd_eeprom_t |
| 421 | spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; |
| 422 | |
| 423 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) |
| 424 | fsl_ddr_get_spd(spd[i], i); |
| 425 | |
| 426 | puts("SPD data of all dimms (zero vaule is omitted)...\n"); |
| 427 | puts("Byte (hex) "); |
| 428 | k = 1; |
| 429 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
| 430 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) |
| 431 | printf("Dimm%d ", k++); |
| 432 | } |
| 433 | puts("\n"); |
| 434 | for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { |
| 435 | m = 0; |
| 436 | printf("%3d (0x%02x) ", k, k); |
| 437 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
| 438 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 439 | p_8 = (u8 *) &spd[i][j]; |
| 440 | if (p_8[k]) { |
| 441 | printf("0x%02x ", p_8[k]); |
| 442 | m++; |
| 443 | } else |
| 444 | puts(" "); |
| 445 | } |
| 446 | } |
| 447 | if (m) |
| 448 | puts("\n"); |
| 449 | else |
| 450 | puts("\r"); |
| 451 | } |
| 452 | |
| 453 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
| 454 | switch (i) { |
| 455 | case 0: |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 456 | ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 457 | break; |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 458 | #if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 459 | case 1: |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 460 | ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 461 | break; |
| 462 | #endif |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 463 | #if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 464 | case 2: |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 465 | ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 466 | break; |
| 467 | #endif |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 468 | #if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 469 | case 3: |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 470 | ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 471 | break; |
| 472 | #endif |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 473 | default: |
| 474 | printf("%s unexpected controller number = %u\n", |
| 475 | __func__, i); |
| 476 | return; |
| 477 | } |
| 478 | } |
| 479 | printf("DDR registers dump for all controllers " |
| 480 | "(zero vaule is omitted)...\n"); |
| 481 | puts("Offset (hex) "); |
| 482 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) |
| 483 | printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); |
| 484 | puts("\n"); |
| 485 | for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { |
| 486 | m = 0; |
| 487 | printf("%6d (0x%04x)", k * 4, k * 4); |
| 488 | for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
| 489 | p_32 = (u32 *) ddr[i]; |
| 490 | if (p_32[k]) { |
| 491 | printf(" 0x%08x", p_32[k]); |
| 492 | m++; |
| 493 | } else |
| 494 | puts(" "); |
| 495 | } |
| 496 | if (m) |
| 497 | puts("\n"); |
| 498 | else |
| 499 | puts("\r"); |
| 500 | } |
| 501 | puts("\n"); |
| 502 | } |
| 503 | |
| 504 | /* invalid the TLBs for DDR and setup new ones to cover p_addr */ |
| 505 | static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) |
| 506 | { |
| 507 | u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 508 | unsigned long epn; |
| 509 | u32 tsize, valid, ptr; |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 510 | int ddr_esel; |
| 511 | |
Becky Bruce | 6969447 | 2011-07-18 18:49:15 -0500 | [diff] [blame] | 512 | clear_ddr_tlbs_phys(p_addr, size>>20); |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 513 | |
| 514 | /* Setup new tlb to cover the physical address */ |
| 515 | setup_ddr_tlbs_phys(p_addr, size>>20); |
| 516 | |
| 517 | ptr = vstart; |
| 518 | ddr_esel = find_tlb_idx((void *)ptr, 1); |
| 519 | if (ddr_esel != -1) { |
| 520 | read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); |
| 521 | } else { |
| 522 | printf("TLB error in function %s\n", __func__); |
| 523 | return -1; |
| 524 | } |
| 525 | |
| 526 | return 0; |
| 527 | } |
| 528 | |
| 529 | /* |
| 530 | * slide the testing window up to test another area |
| 531 | * for 32_bit system, the maximum testable memory is limited to |
| 532 | * CONFIG_MAX_MEM_MAPPED |
| 533 | */ |
| 534 | int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 535 | { |
| 536 | phys_addr_t test_cap, p_addr; |
| 537 | phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); |
| 538 | |
| 539 | #if !defined(CONFIG_PHYS_64BIT) || \ |
| 540 | !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ |
| 541 | (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) |
| 542 | test_cap = p_size; |
| 543 | #else |
| 544 | test_cap = gd->ram_size; |
| 545 | #endif |
| 546 | p_addr = (*vstart) + (*size) + (*phys_offset); |
| 547 | if (p_addr < test_cap - 1) { |
| 548 | p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); |
| 549 | if (reset_tlb(p_addr, p_size, phys_offset) == -1) |
| 550 | return -1; |
| 551 | *vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 552 | *size = (u32) p_size; |
| 553 | printf("Testing 0x%08llx - 0x%08llx\n", |
| 554 | (u64)(*vstart) + (*phys_offset), |
| 555 | (u64)(*vstart) + (*phys_offset) + (*size) - 1); |
| 556 | } else |
| 557 | return 1; |
| 558 | |
| 559 | return 0; |
| 560 | } |
| 561 | |
| 562 | /* initialization for testing area */ |
| 563 | int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 564 | { |
| 565 | phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); |
| 566 | |
| 567 | *vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 568 | *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ |
| 569 | *phys_offset = 0; |
| 570 | |
| 571 | #if !defined(CONFIG_PHYS_64BIT) || \ |
| 572 | !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ |
| 573 | (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) |
| 574 | if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { |
| 575 | puts("Cannot test more than "); |
| 576 | print_size(CONFIG_MAX_MEM_MAPPED, |
| 577 | " without proper 36BIT support.\n"); |
| 578 | } |
| 579 | #endif |
| 580 | printf("Testing 0x%08llx - 0x%08llx\n", |
| 581 | (u64)(*vstart) + (*phys_offset), |
| 582 | (u64)(*vstart) + (*phys_offset) + (*size) - 1); |
| 583 | |
| 584 | return 0; |
| 585 | } |
| 586 | |
| 587 | /* invalid TLBs for DDR and remap as normal after testing */ |
| 588 | int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 589 | { |
| 590 | unsigned long epn; |
| 591 | u32 tsize, valid, ptr; |
| 592 | phys_addr_t rpn = 0; |
| 593 | int ddr_esel; |
| 594 | |
| 595 | /* disable the TLBs for this testing */ |
| 596 | ptr = *vstart; |
| 597 | |
| 598 | while (ptr < (*vstart) + (*size)) { |
| 599 | ddr_esel = find_tlb_idx((void *)ptr, 1); |
| 600 | if (ddr_esel != -1) { |
| 601 | read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); |
| 602 | disable_tlb(ddr_esel); |
| 603 | } |
| 604 | ptr += TSIZE_TO_BYTES(tsize); |
| 605 | } |
| 606 | |
| 607 | puts("Remap DDR "); |
| 608 | setup_ddr_tlbs(gd->ram_size>>20); |
| 609 | puts("\n"); |
| 610 | |
| 611 | return 0; |
| 612 | } |
| 613 | |
| 614 | void arch_memory_failure_handle(void) |
| 615 | { |
| 616 | dump_spd_ddr_reg(); |
| 617 | } |
| 618 | #endif |