Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 6e5c0191c04df1913982bc1a335863db82936578 / . / configs / puma-rk3399_defconfig
blob: a8b4bacbecf24b429dbf0a951b6a4a452cfbad11 [file] [log] [blame]
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00200000
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]4CONFIG_SPL_GPIO_SUPPORT=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]5CONFIG_SPL_LIBCOMMON_SUPPORT=y
6CONFIG_SPL_LIBGENERIC_SUPPORT=y
7CONFIG_SYS_MALLOC_F_LEN=0x4000
8CONFIG_ROCKCHIP_RK3399=y
Philipp Tomsich7427c392017-11-24 14:44:59 +0100[diff] [blame]9CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
Tom Rini79f4eea2017-05-01 11:41:11 -0400[diff] [blame]10CONFIG_TARGET_PUMA_RK3399=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]11CONFIG_SPL_SPI_FLASH_SUPPORT=y
12CONFIG_SPL_SPI_SUPPORT=y
13CONFIG_SPL_STACK_R_ADDR=0x80000
Philipp Tomsich962466d2017-06-06 20:44:45 +0200[diff] [blame]14CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600"
Philipp Tomsicha4dbfc32017-05-31 18:18:49 +0200[diff] [blame]15CONFIG_DEBUG_UART=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]16CONFIG_FIT=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]17CONFIG_SPL_LOAD_FIT=y
Philipp Tomsich9eefd0f2017-05-05 19:22:54 +0200[diff] [blame]18CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its"
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]19# CONFIG_DISPLAY_CPUINFO is not set
Philipp Tomsicheade1642017-06-07 18:13:42 +0200[diff] [blame]20CONFIG_SPL_BOARD_INIT=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]21# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
22# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
23CONFIG_SPL_STACK_R=y
24CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
25CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]26CONFIG_SPL_I2C_SUPPORT=y
27CONFIG_SPL_POWER_SUPPORT=y
Philipp Tomsichf9413732017-09-13 21:29:42 +0200[diff] [blame]28CONFIG_SPL_ATF=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]29CONFIG_CMD_BOOTZ=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]30CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]31CONFIG_CMD_I2C=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]32CONFIG_CMD_MMC=y
33CONFIG_CMD_SF=y
34CONFIG_CMD_SPI=y
35CONFIG_CMD_USB=y
36# CONFIG_CMD_SETEXPR is not set
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]37CONFIG_CMD_BMP=y
38CONFIG_CMD_CACHE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]39CONFIG_CMD_TIME=y
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]40CONFIG_CMD_PMIC=y
41CONFIG_CMD_REGULATOR=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]42CONFIG_SPL_OF_CONTROL=y
Philipp Tomsich00fd83f2017-09-12 17:32:29 +0200[diff] [blame]43CONFIG_OF_LIVE=y
Philipp Tomsich57806cb2017-05-31 18:18:50 +0200[diff] [blame]44CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]45CONFIG_ENV_IS_IN_MMC=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]46CONFIG_REGMAP=y
47CONFIG_SPL_REGMAP=y
48CONFIG_SYSCON=y
49CONFIG_SPL_SYSCON=y
50CONFIG_CLK=y
51CONFIG_SPL_CLK=y
52CONFIG_ROCKCHIP_GPIO=y
Philipp Tomsicha4dbfc32017-05-31 18:18:49 +0200[diff] [blame]53CONFIG_SYS_I2C_ROCKCHIP=y
Philipp Tomsichf781e802017-05-05 19:21:41 +0200[diff] [blame]54CONFIG_MISC=y
55CONFIG_ROCKCHIP_EFUSE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]56CONFIG_MMC_DW=y
57CONFIG_MMC_DW_ROCKCHIP=y
58CONFIG_MMC_SDHCI=y
59CONFIG_MMC_SDHCI_ROCKCHIP=y
60CONFIG_SPI_FLASH=y
61CONFIG_SPI_FLASH_WINBOND=y
62CONFIG_PHY_MICREL=y
Philipp Tomsich87321152017-10-30 14:44:55 +0100[diff] [blame]63CONFIG_PHY_MICREL_KSZ90X1=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]64CONFIG_DM_ETH=y
65CONFIG_ETH_DESIGNWARE=y
66CONFIG_GMAC_ROCKCHIP=y
67CONFIG_PINCTRL=y
68CONFIG_SPL_PINCTRL=y
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]69CONFIG_PINCTRL_ROCKCHIP_RK3399=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]70CONFIG_DM_PMIC=y
71CONFIG_PMIC_RK8XX=y
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]72CONFIG_SPL_DM_REGULATOR=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]73CONFIG_DM_REGULATOR_FIXED=y
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]74CONFIG_SPL_DM_REGULATOR_FIXED=y
75CONFIG_DM_REGULATOR_GPIO=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]76CONFIG_REGULATOR_RK8XX=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]77CONFIG_PWM_ROCKCHIP=y
78CONFIG_RAM=y
79CONFIG_SPL_RAM=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]80CONFIG_DEBUG_UART_BASE=0xFF180000
81CONFIG_DEBUG_UART_CLOCK=24000000
82CONFIG_DEBUG_UART_SHIFT=2
83CONFIG_SYS_NS16550=y
84CONFIG_ROCKCHIP_SPI=y
85CONFIG_SYSRESET=y
86CONFIG_USB=y
87CONFIG_USB_XHCI_HCD=y
88CONFIG_USB_XHCI_DWC3=y
89CONFIG_USB_EHCI_HCD=y
90CONFIG_USB_EHCI_GENERIC=y
91CONFIG_USB_STORAGE=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]92CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]93CONFIG_USB_ETHER_ASIX=y
94CONFIG_USB_ETHER_ASIX88179=y
95CONFIG_USB_ETHER_MCS7830=y
96CONFIG_USB_ETHER_RTL8152=y
97CONFIG_USB_ETHER_SMSC95XX=y
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]98CONFIG_DM_VIDEO=y
99CONFIG_DISPLAY=y
100CONFIG_VIDEO_ROCKCHIP=y
101CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]102CONFIG_ERRNO_STR=y