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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk9c53f402003-10-15 23:53:47 +00002/*
wdenka445ddf2004-06-09 00:34:46 +00003 * Freescale Three Speed Ethernet Controller driver
wdenk9c53f402003-10-15 23:53:47 +00004 *
Claudiu Manoilcd0c4122013-09-30 12:44:42 +03005 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
wdenk9c53f402003-10-15 23:53:47 +00006 * (C) Copyright 2003, Motorola, Inc.
wdenk9c53f402003-10-15 23:53:47 +00007 * author Andy Fleming
wdenk9c53f402003-10-15 23:53:47 +00008 */
9
10#include <config.h>
wdenk9c53f402003-10-15 23:53:47 +000011#include <common.h>
Bin Meng1048f612016-01-11 22:41:24 -080012#include <dm.h>
wdenk9c53f402003-10-15 23:53:47 +000013#include <malloc.h>
14#include <net.h>
15#include <command.h>
Andy Flemingc067fc12008-08-31 16:33:25 -050016#include <tsec.h>
Andy Fleming422effd2011-04-08 02:10:54 -050017#include <fsl_mdio.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060018#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060019#include <linux/delay.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090020#include <linux/errno.h>
Hou Zhiqiangd35de972020-07-16 18:09:12 +080021#include <miiphy.h>
chenhui zhaoc8caa8a2011-10-03 08:38:50 -050022#include <asm/processor.h>
Alison Wang32cc5912014-09-05 13:52:38 +080023#include <asm/io.h>
wdenk9c53f402003-10-15 23:53:47 +000024
Andy Flemingac65e072008-08-31 16:33:27 -050025#define TBIANA_SETTINGS ( \
26 TBIANA_ASYMMETRIC_PAUSE \
27 | TBIANA_SYMMETRIC_PAUSE \
28 | TBIANA_FULL_DUPLEX \
29 )
30
Felix Radensky27f98e02010-06-28 01:57:39 +030031/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
32#ifndef CONFIG_TSEC_TBICR_SETTINGS
Kumar Galac1457f92010-12-01 22:55:54 -060033#define CONFIG_TSEC_TBICR_SETTINGS ( \
Andy Flemingac65e072008-08-31 16:33:27 -050034 TBICR_PHY_RESET \
Kumar Galac1457f92010-12-01 22:55:54 -060035 | TBICR_ANEG_ENABLE \
Andy Flemingac65e072008-08-31 16:33:27 -050036 | TBICR_FULL_DUPLEX \
37 | TBICR_SPEED1_SET \
38 )
Felix Radensky27f98e02010-06-28 01:57:39 +030039#endif /* CONFIG_TSEC_TBICR_SETTINGS */
Peter Tyser583c1f42009-11-03 17:52:07 -060040
Andy Flemingac65e072008-08-31 16:33:27 -050041/* Configure the TBI for SGMII operation */
42static void tsec_configure_serdes(struct tsec_private *priv)
43{
Bin Meng79cd33a2016-01-11 22:41:18 -080044 /*
45 * Access TBI PHY registers at given TSEC register offset as opposed
46 * to the register offset used for external PHY accesses
47 */
Andy Fleming422effd2011-04-08 02:10:54 -050048 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixc29fcc72018-01-15 11:08:21 +010049 0, TBI_ANA, TBIANA_SETTINGS);
Andy Fleming422effd2011-04-08 02:10:54 -050050 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixc29fcc72018-01-15 11:08:21 +010051 0, TBI_TBICON, TBICON_CLK_SELECT);
Andy Fleming422effd2011-04-08 02:10:54 -050052 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixc29fcc72018-01-15 11:08:21 +010053 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
David Updegraff0451b012007-04-20 14:34:48 -050054}
55
Chris Packhambbe18572018-11-26 21:00:28 +130056/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
57 * and this is the ethernet-crc method needed for TSEC -- and perhaps
58 * some other adapter -- hash tables
59 */
60#define CRCPOLY_LE 0xedb88320
61static u32 ether_crc(size_t len, unsigned char const *p)
62{
63 int i;
64 u32 crc;
65
66 crc = ~0;
67 while (len--) {
68 crc ^= *p++;
69 for (i = 0; i < 8; i++)
70 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
71 }
72 /* an reverse the bits, cuz of way they arrive -- last-first */
73 crc = (crc >> 16) | (crc << 16);
74 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
75 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
76 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
77 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
78 return crc;
79}
80
Mingkai Hue0653bf2011-01-27 12:52:46 +080081/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
82
83/* Set the appropriate hash bit for the given addr */
84
Bin Meng79cd33a2016-01-11 22:41:18 -080085/*
86 * The algorithm works like so:
Mingkai Hue0653bf2011-01-27 12:52:46 +080087 * 1) Take the Destination Address (ie the multicast address), and
88 * do a CRC on it (little endian), and reverse the bits of the
89 * result.
90 * 2) Use the 8 most significant bits as a hash into a 256-entry
91 * table. The table is controlled through 8 32-bit registers:
Claudiu Manoil461511b2013-09-30 12:44:40 +030092 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
93 * 255. This means that the 3 most significant bits in the
Mingkai Hue0653bf2011-01-27 12:52:46 +080094 * hash index which gaddr register to use, and the 5 other bits
95 * indicate which bit (assuming an IBM numbering scheme, which
Claudiu Manoil461511b2013-09-30 12:44:40 +030096 * for PowerPC (tm) is usually the case) in the register holds
Bin Meng79cd33a2016-01-11 22:41:18 -080097 * the entry.
98 */
Chris Packhama55ef7f2018-11-26 21:00:29 +130099static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
Mingkai Hue0653bf2011-01-27 12:52:46 +0800100{
Simon Glass95588622020-12-22 19:30:28 -0700101 struct tsec_private *priv;
102 struct tsec __iomem *regs;
Claudiu Manoil461511b2013-09-30 12:44:40 +0300103 u32 result, value;
104 u8 whichbit, whichreg;
Mingkai Hue0653bf2011-01-27 12:52:46 +0800105
Simon Glass95588622020-12-22 19:30:28 -0700106 priv = dev_get_priv(dev);
Simon Glass95588622020-12-22 19:30:28 -0700107 regs = priv->regs;
Claudiu Manoil461511b2013-09-30 12:44:40 +0300108 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
109 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
110 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
Mingkai Hue0653bf2011-01-27 12:52:46 +0800111
Mario Sixc29fcc72018-01-15 11:08:21 +0100112 value = BIT(31 - whichbit);
Claudiu Manoil461511b2013-09-30 12:44:40 +0300113
Chris Packhama55ef7f2018-11-26 21:00:29 +1300114 if (join)
Claudiu Manoil461511b2013-09-30 12:44:40 +0300115 setbits_be32(&regs->hash.gaddr0 + whichreg, value);
116 else
117 clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800118
Mingkai Hue0653bf2011-01-27 12:52:46 +0800119 return 0;
120}
Mingkai Hue0653bf2011-01-27 12:52:46 +0800121
Tom Rini5c1b0712022-12-13 09:26:25 -0500122static int tsec_set_promisc(struct udevice *dev, bool enable)
Vladimir Oltean3556c4d2021-09-29 18:04:36 +0300123{
124 struct tsec_private *priv = dev_get_priv(dev);
125 struct tsec __iomem *regs = priv->regs;
126
127 if (enable)
128 setbits_be32(&regs->rctrl, RCTRL_PROM);
129 else
130 clrbits_be32(&regs->rctrl, RCTRL_PROM);
131
132 return 0;
133}
134
Bin Meng79cd33a2016-01-11 22:41:18 -0800135/*
136 * Initialized required registers to appropriate values, zeroing
Mingkai Hue0653bf2011-01-27 12:52:46 +0800137 * those we don't care about (unless zero is bad, in which case,
138 * choose a more appropriate value)
139 */
Claudiu Manoilcd0c4122013-09-30 12:44:42 +0300140static void init_registers(struct tsec __iomem *regs)
Mingkai Hue0653bf2011-01-27 12:52:46 +0800141{
142 /* Clear IEVENT */
143 out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
144
145 out_be32(&regs->imask, IMASK_INIT_CLEAR);
146
147 out_be32(&regs->hash.iaddr0, 0);
148 out_be32(&regs->hash.iaddr1, 0);
149 out_be32(&regs->hash.iaddr2, 0);
150 out_be32(&regs->hash.iaddr3, 0);
151 out_be32(&regs->hash.iaddr4, 0);
152 out_be32(&regs->hash.iaddr5, 0);
153 out_be32(&regs->hash.iaddr6, 0);
154 out_be32(&regs->hash.iaddr7, 0);
155
156 out_be32(&regs->hash.gaddr0, 0);
157 out_be32(&regs->hash.gaddr1, 0);
158 out_be32(&regs->hash.gaddr2, 0);
159 out_be32(&regs->hash.gaddr3, 0);
160 out_be32(&regs->hash.gaddr4, 0);
161 out_be32(&regs->hash.gaddr5, 0);
162 out_be32(&regs->hash.gaddr6, 0);
163 out_be32(&regs->hash.gaddr7, 0);
164
Mingkai Hue0653bf2011-01-27 12:52:46 +0800165 /* Init RMON mib registers */
Claudiu Manoila18ab902013-09-30 12:44:46 +0300166 memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
Mingkai Hue0653bf2011-01-27 12:52:46 +0800167
168 out_be32(&regs->rmon.cam1, 0xffffffff);
169 out_be32(&regs->rmon.cam2, 0xffffffff);
170
171 out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
172
173 out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
174
175 out_be32(&regs->attr, ATTR_INIT_SETTINGS);
176 out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800177}
178
Bin Meng79cd33a2016-01-11 22:41:18 -0800179/*
180 * Configure maccfg2 based on negotiated speed and duplex
Mingkai Hue0653bf2011-01-27 12:52:46 +0800181 * reported by PHY handling code
182 */
Andy Fleming422effd2011-04-08 02:10:54 -0500183static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
Mingkai Hue0653bf2011-01-27 12:52:46 +0800184{
Claudiu Manoilcd0c4122013-09-30 12:44:42 +0300185 struct tsec __iomem *regs = priv->regs;
Mingkai Hue0653bf2011-01-27 12:52:46 +0800186 u32 ecntrl, maccfg2;
187
Andy Fleming422effd2011-04-08 02:10:54 -0500188 if (!phydev->link) {
189 printf("%s: No link.\n", phydev->dev->name);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800190 return;
191 }
192
193 /* clear all bits relative with interface mode */
194 ecntrl = in_be32(&regs->ecntrl);
195 ecntrl &= ~ECNTRL_R100;
196
197 maccfg2 = in_be32(&regs->maccfg2);
198 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
199
Andy Fleming422effd2011-04-08 02:10:54 -0500200 if (phydev->duplex)
Mingkai Hue0653bf2011-01-27 12:52:46 +0800201 maccfg2 |= MACCFG2_FULL_DUPLEX;
202
Andy Fleming422effd2011-04-08 02:10:54 -0500203 switch (phydev->speed) {
Mingkai Hue0653bf2011-01-27 12:52:46 +0800204 case 1000:
205 maccfg2 |= MACCFG2_GMII;
206 break;
207 case 100:
208 case 10:
209 maccfg2 |= MACCFG2_MII;
210
Bin Meng79cd33a2016-01-11 22:41:18 -0800211 /*
212 * Set R100 bit in all modes although
Mingkai Hue0653bf2011-01-27 12:52:46 +0800213 * it is only used in RGMII mode
214 */
Andy Fleming422effd2011-04-08 02:10:54 -0500215 if (phydev->speed == 100)
Mingkai Hue0653bf2011-01-27 12:52:46 +0800216 ecntrl |= ECNTRL_R100;
217 break;
218 default:
Andy Fleming422effd2011-04-08 02:10:54 -0500219 printf("%s: Speed was bad\n", phydev->dev->name);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800220 break;
221 }
222
223 out_be32(&regs->ecntrl, ecntrl);
224 out_be32(&regs->maccfg2, maccfg2);
wdenkf41ff3b2005-04-04 23:43:44 +0000225
Andy Fleming422effd2011-04-08 02:10:54 -0500226 printf("Speed: %d, %s duplex%s\n", phydev->speed,
Mario Sixc29fcc72018-01-15 11:08:21 +0100227 (phydev->duplex) ? "full" : "half",
228 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
Mingkai Hue0653bf2011-01-27 12:52:46 +0800229}
wdenkbfad55d2005-03-14 23:56:42 +0000230
Bin Meng80b1a1c2016-01-11 22:41:21 -0800231/*
232 * This returns the status bits of the device. The return value
233 * is never checked, and this is what the 8260 driver did, so we
234 * do the same. Presumably, this would be zero if there were no
235 * errors
236 */
Bin Meng1048f612016-01-11 22:41:24 -0800237static int tsec_send(struct udevice *dev, void *packet, int length)
Bin Meng80b1a1c2016-01-11 22:41:21 -0800238{
Simon Glass95588622020-12-22 19:30:28 -0700239 struct tsec_private *priv;
240 struct tsec __iomem *regs;
Bin Meng80b1a1c2016-01-11 22:41:21 -0800241 int result = 0;
Vladimir Olteana11c89d2019-07-19 00:29:55 +0300242 u16 status;
Bin Meng80b1a1c2016-01-11 22:41:21 -0800243 int i;
244
Simon Glass95588622020-12-22 19:30:28 -0700245 priv = dev_get_priv(dev);
Simon Glass95588622020-12-22 19:30:28 -0700246 regs = priv->regs;
Bin Meng80b1a1c2016-01-11 22:41:21 -0800247 /* Find an empty buffer descriptor */
248 for (i = 0;
249 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
250 i++) {
251 if (i >= TOUT_LOOP) {
Vladimir Oltean8ec8eaa2019-07-19 00:29:56 +0300252 printf("%s: tsec: tx buffers full\n", dev->name);
Bin Meng80b1a1c2016-01-11 22:41:21 -0800253 return result;
254 }
255 }
256
257 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
258 out_be16(&priv->txbd[priv->tx_idx].length, length);
259 status = in_be16(&priv->txbd[priv->tx_idx].status);
260 out_be16(&priv->txbd[priv->tx_idx].status, status |
261 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
262
263 /* Tell the DMA to go */
264 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
265
266 /* Wait for buffer to be transmitted */
267 for (i = 0;
268 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
269 i++) {
270 if (i >= TOUT_LOOP) {
Vladimir Oltean8ec8eaa2019-07-19 00:29:56 +0300271 printf("%s: tsec: tx error\n", dev->name);
Bin Meng80b1a1c2016-01-11 22:41:21 -0800272 return result;
273 }
274 }
275
276 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
277 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
278
279 return result;
280}
281
Bin Meng1048f612016-01-11 22:41:24 -0800282static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
283{
Simon Glass95588622020-12-22 19:30:28 -0700284 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
Bin Meng1048f612016-01-11 22:41:24 -0800285 struct tsec __iomem *regs = priv->regs;
286 int ret = -1;
287
288 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
289 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
Mario Sixc29fcc72018-01-15 11:08:21 +0100290 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
291 u32 buf;
Bin Meng1048f612016-01-11 22:41:24 -0800292
293 /* Send the packet up if there were no errors */
294 if (!(status & RXBD_STATS)) {
295 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
296 *packetp = (uchar *)buf;
297 ret = length - 4;
298 } else {
299 printf("Got error %x\n", (status & RXBD_STATS));
300 }
301 }
302
303 if (in_be32(&regs->ievent) & IEVENT_BSY) {
304 out_be32(&regs->ievent, IEVENT_BSY);
305 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
306 }
307
308 return ret;
309}
310
311static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
312{
Simon Glass95588622020-12-22 19:30:28 -0700313 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
Mario Sixc29fcc72018-01-15 11:08:21 +0100314 u16 status;
Bin Meng1048f612016-01-11 22:41:24 -0800315
316 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
317
318 status = RXBD_EMPTY;
319 /* Set the wrap bit if this is the last element in the list */
320 if ((priv->rx_idx + 1) == PKTBUFSRX)
321 status |= RXBD_WRAP;
322 out_be16(&priv->rxbd[priv->rx_idx].status, status);
323
324 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
325
326 return 0;
327}
Bin Meng80b1a1c2016-01-11 22:41:21 -0800328
Bin Meng1048f612016-01-11 22:41:24 -0800329static void tsec_halt(struct udevice *dev)
Bin Meng80b1a1c2016-01-11 22:41:21 -0800330{
Simon Glass95588622020-12-22 19:30:28 -0700331 struct tsec_private *priv;
332 struct tsec __iomem *regs;
Simon Glass95588622020-12-22 19:30:28 -0700333 priv = dev_get_priv(dev);
Simon Glass95588622020-12-22 19:30:28 -0700334 regs = priv->regs;
Bin Meng80b1a1c2016-01-11 22:41:21 -0800335
336 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
337 setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
338
339 while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
340 != (IEVENT_GRSC | IEVENT_GTSC))
341 ;
342
343 clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
344
345 /* Shut down the PHY, as needed */
346 phy_shutdown(priv->phydev);
347}
348
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500349#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
350/*
351 * When MACCFG1[Rx_EN] is enabled during system boot as part
352 * of the eTSEC port initialization sequence,
353 * the eTSEC Rx logic may not be properly initialized.
354 */
Bin Meng18864072021-11-01 14:15:12 +0800355static void redundant_init(struct tsec_private *priv)
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500356{
Claudiu Manoilcd0c4122013-09-30 12:44:42 +0300357 struct tsec __iomem *regs = priv->regs;
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500358 uint t, count = 0;
359 int fail = 1;
360 static const u8 pkt[] = {
361 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
362 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
363 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
364 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
365 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
366 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
367 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
368 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
369 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
370 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
371 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
372 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
373 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
374 0x71, 0x72};
375
376 /* Enable promiscuous mode */
Vladimir Oltean3556c4d2021-09-29 18:04:36 +0300377 setbits_be32(&regs->rctrl, RCTRL_PROM);
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500378 /* Enable loopback mode */
379 setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
380 /* Enable transmit and receive */
381 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
382
383 /* Tell the DMA it is clear to go */
384 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
385 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
386 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
387 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
388
389 do {
Mario Sixc29fcc72018-01-15 11:08:21 +0100390 u16 status;
391
Bin Menge86a6cd2016-01-11 22:41:22 -0800392 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500393
394 /* Wait for buffer to be received */
Bin Meng1120c542016-01-11 22:41:20 -0800395 for (t = 0;
396 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
Bin Meng76f53992016-01-11 22:41:19 -0800397 t++) {
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500398 if (t >= 10 * TOUT_LOOP) {
Bin Menge86a6cd2016-01-11 22:41:22 -0800399 printf("%s: tsec: rx error\n", priv->dev->name);
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500400 break;
401 }
402 }
403
Bin Meng76f53992016-01-11 22:41:19 -0800404 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500405 fail = 0;
406
Bin Meng1120c542016-01-11 22:41:20 -0800407 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
Claudiu Manoileec416b2013-10-04 19:13:53 +0300408 status = RXBD_EMPTY;
Bin Meng76f53992016-01-11 22:41:19 -0800409 if ((priv->rx_idx + 1) == PKTBUFSRX)
Claudiu Manoileec416b2013-10-04 19:13:53 +0300410 status |= RXBD_WRAP;
Bin Meng1120c542016-01-11 22:41:20 -0800411 out_be16(&priv->rxbd[priv->rx_idx].status, status);
Bin Meng76f53992016-01-11 22:41:19 -0800412 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500413
414 if (in_be32(&regs->ievent) & IEVENT_BSY) {
415 out_be32(&regs->ievent, IEVENT_BSY);
416 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
417 }
418 if (fail) {
419 printf("loopback recv packet error!\n");
420 clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
421 udelay(1000);
422 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
423 }
424 } while ((count++ < 4) && (fail == 1));
425
426 if (fail)
427 panic("eTSEC init fail!\n");
428 /* Disable promiscuous mode */
Vladimir Oltean3556c4d2021-09-29 18:04:36 +0300429 clrbits_be32(&regs->rctrl, RCTRL_PROM);
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500430 /* Disable loopback mode */
431 clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
432}
433#endif
434
Bin Meng79cd33a2016-01-11 22:41:18 -0800435/*
436 * Set up the buffers and their descriptors, and bring up the
Mingkai Hue0653bf2011-01-27 12:52:46 +0800437 * interface
Jon Loeligerb7ced082006-10-10 17:03:43 -0500438 */
Bin Menge86a6cd2016-01-11 22:41:22 -0800439static void startup_tsec(struct tsec_private *priv)
Wolfgang Denkf0c4e462006-03-12 22:50:55 +0100440{
Claudiu Manoilcd0c4122013-09-30 12:44:42 +0300441 struct tsec __iomem *regs = priv->regs;
Mario Sixc29fcc72018-01-15 11:08:21 +0100442 u16 status;
Claudiu Manoileec416b2013-10-04 19:13:53 +0300443 int i;
Wolfgang Denkf0c4e462006-03-12 22:50:55 +0100444
Andy Fleming422effd2011-04-08 02:10:54 -0500445 /* reset the indices to zero */
Bin Meng76f53992016-01-11 22:41:19 -0800446 priv->rx_idx = 0;
447 priv->tx_idx = 0;
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500448#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
449 uint svr;
450#endif
Andy Fleming422effd2011-04-08 02:10:54 -0500451
Mingkai Hue0653bf2011-01-27 12:52:46 +0800452 /* Point to the buffer descriptors */
Bin Meng1120c542016-01-11 22:41:20 -0800453 out_be32(&regs->tbase, (u32)&priv->txbd[0]);
454 out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
Wolfgang Denkf0c4e462006-03-12 22:50:55 +0100455
Mingkai Hue0653bf2011-01-27 12:52:46 +0800456 /* Initialize the Rx Buffer descriptors */
457 for (i = 0; i < PKTBUFSRX; i++) {
Bin Meng1120c542016-01-11 22:41:20 -0800458 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
459 out_be16(&priv->rxbd[i].length, 0);
460 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800461 }
Bin Meng1120c542016-01-11 22:41:20 -0800462 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
463 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
Wolfgang Denkf0c4e462006-03-12 22:50:55 +0100464
Mingkai Hue0653bf2011-01-27 12:52:46 +0800465 /* Initialize the TX Buffer Descriptors */
466 for (i = 0; i < TX_BUF_CNT; i++) {
Bin Meng1120c542016-01-11 22:41:20 -0800467 out_be16(&priv->txbd[i].status, 0);
468 out_be16(&priv->txbd[i].length, 0);
469 out_be32(&priv->txbd[i].bufptr, 0);
Wolfgang Denkf0c4e462006-03-12 22:50:55 +0100470 }
Bin Meng1120c542016-01-11 22:41:20 -0800471 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
472 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
Wolfgang Denkf0c4e462006-03-12 22:50:55 +0100473
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500474#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
475 svr = get_svr();
476 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
Bin Menge86a6cd2016-01-11 22:41:22 -0800477 redundant_init(priv);
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500478#endif
Mingkai Hue0653bf2011-01-27 12:52:46 +0800479 /* Enable Transmit and Receive */
480 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
481
482 /* Tell the DMA it is clear to go */
483 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
484 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
485 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
486 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
Wolfgang Denkf0c4e462006-03-12 22:50:55 +0100487}
488
Bin Meng79cd33a2016-01-11 22:41:18 -0800489/*
Bin Meng79cd33a2016-01-11 22:41:18 -0800490 * Initializes data structures and registers for the controller,
491 * and brings the interface up. Returns the link status, meaning
Mingkai Hue0653bf2011-01-27 12:52:46 +0800492 * that it returns success if the link is up, failure otherwise.
Bin Meng79cd33a2016-01-11 22:41:18 -0800493 * This allows U-Boot to find the first active controller.
Jon Loeligerb7ced082006-10-10 17:03:43 -0500494 */
Bin Meng1048f612016-01-11 22:41:24 -0800495static int tsec_init(struct udevice *dev)
wdenka445ddf2004-06-09 00:34:46 +0000496{
Simon Glass95588622020-12-22 19:30:28 -0700497 struct tsec_private *priv;
498 struct tsec __iomem *regs;
Simon Glassfa20e932020-12-03 16:55:20 -0700499 struct eth_pdata *pdata = dev_get_plat(dev);
Claudiu Manoildcb38fe2013-09-30 12:44:47 +0300500 u32 tempval;
Timur Tabi42387462012-07-09 08:52:43 +0000501 int ret;
wdenka445ddf2004-06-09 00:34:46 +0000502
Simon Glass95588622020-12-22 19:30:28 -0700503 priv = dev_get_priv(dev);
Simon Glass95588622020-12-22 19:30:28 -0700504 regs = priv->regs;
Mingkai Hue0653bf2011-01-27 12:52:46 +0800505 /* Make sure the controller is stopped */
506 tsec_halt(dev);
wdenka445ddf2004-06-09 00:34:46 +0000507
Mingkai Hue0653bf2011-01-27 12:52:46 +0800508 /* Init MACCFG2. Defaults to GMII */
509 out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
wdenka445ddf2004-06-09 00:34:46 +0000510
Mingkai Hue0653bf2011-01-27 12:52:46 +0800511 /* Init ECNTRL */
512 out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
wdenka445ddf2004-06-09 00:34:46 +0000513
Bin Meng79cd33a2016-01-11 22:41:18 -0800514 /*
515 * Copy the station address into the address registers.
Claudiu Manoildcb38fe2013-09-30 12:44:47 +0300516 * For a station address of 0x12345678ABCD in transmission
517 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
518 * MACnADDR2 is set to 0x34120000.
519 */
Bin Meng1048f612016-01-11 22:41:24 -0800520 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
521 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
wdenka445ddf2004-06-09 00:34:46 +0000522
Mingkai Hue0653bf2011-01-27 12:52:46 +0800523 out_be32(&regs->macstnaddr1, tempval);
wdenka445ddf2004-06-09 00:34:46 +0000524
Bin Meng1048f612016-01-11 22:41:24 -0800525 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
wdenka445ddf2004-06-09 00:34:46 +0000526
Mingkai Hue0653bf2011-01-27 12:52:46 +0800527 out_be32(&regs->macstnaddr2, tempval);
wdenka445ddf2004-06-09 00:34:46 +0000528
Mingkai Hue0653bf2011-01-27 12:52:46 +0800529 /* Clear out (for the most part) the other registers */
530 init_registers(regs);
531
532 /* Ready the device for tx/rx */
Bin Menge86a6cd2016-01-11 22:41:22 -0800533 startup_tsec(priv);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800534
Andy Fleming422effd2011-04-08 02:10:54 -0500535 /* Start up the PHY */
Timur Tabi42387462012-07-09 08:52:43 +0000536 ret = phy_startup(priv->phydev);
537 if (ret) {
538 printf("Could not initialize PHY %s\n",
539 priv->phydev->dev->name);
540 return ret;
541 }
Andy Fleming422effd2011-04-08 02:10:54 -0500542
543 adjust_link(priv, priv->phydev);
544
Mingkai Hue0653bf2011-01-27 12:52:46 +0800545 /* If there's no link, fail */
Andy Fleming422effd2011-04-08 02:10:54 -0500546 return priv->phydev->link ? 0 : -1;
547}
548
Ramon Fried8ca1e6b2021-09-28 18:49:02 +0300549static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
Andy Fleming422effd2011-04-08 02:10:54 -0500550{
Claudiu Manoilcd0c4122013-09-30 12:44:42 +0300551 struct tsec __iomem *regs = priv->regs;
Andy Fleming422effd2011-04-08 02:10:54 -0500552 u32 ecntrl;
553
554 ecntrl = in_be32(&regs->ecntrl);
555
556 if (ecntrl & ECNTRL_SGMII_MODE)
557 return PHY_INTERFACE_MODE_SGMII;
558
559 if (ecntrl & ECNTRL_TBI_MODE) {
560 if (ecntrl & ECNTRL_REDUCED_MODE)
561 return PHY_INTERFACE_MODE_RTBI;
562 else
563 return PHY_INTERFACE_MODE_TBI;
564 }
565
566 if (ecntrl & ECNTRL_REDUCED_MODE) {
Mario Sixc29fcc72018-01-15 11:08:21 +0100567 phy_interface_t interface;
568
Andy Fleming422effd2011-04-08 02:10:54 -0500569 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
570 return PHY_INTERFACE_MODE_RMII;
Andy Fleming422effd2011-04-08 02:10:54 -0500571
Mario Sixc29fcc72018-01-15 11:08:21 +0100572 interface = priv->interface;
Andy Fleming422effd2011-04-08 02:10:54 -0500573
Mario Sixc29fcc72018-01-15 11:08:21 +0100574 /*
575 * This isn't autodetected, so it must
576 * be set by the platform code.
577 */
578 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
579 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
580 interface == PHY_INTERFACE_MODE_RGMII_RXID)
581 return interface;
582
583 return PHY_INTERFACE_MODE_RGMII;
Andy Fleming422effd2011-04-08 02:10:54 -0500584 }
585
586 if (priv->flags & TSEC_GIGABIT)
587 return PHY_INTERFACE_MODE_GMII;
588
589 return PHY_INTERFACE_MODE_MII;
Mingkai Hue0653bf2011-01-27 12:52:46 +0800590}
591
Bin Meng79cd33a2016-01-11 22:41:18 -0800592/*
593 * Discover which PHY is attached to the device, and configure it
Mingkai Hue0653bf2011-01-27 12:52:46 +0800594 * properly. If the PHY is not recognized, then return 0
595 * (failure). Otherwise, return 1
wdenk78924a72004-04-18 21:45:42 +0000596 */
Bin Menge86a6cd2016-01-11 22:41:22 -0800597static int init_phy(struct tsec_private *priv)
wdenk78924a72004-04-18 21:45:42 +0000598{
Andy Fleming422effd2011-04-08 02:10:54 -0500599 struct phy_device *phydev;
Claudiu Manoilcd0c4122013-09-30 12:44:42 +0300600 struct tsec __iomem *regs = priv->regs;
Andy Fleming422effd2011-04-08 02:10:54 -0500601 u32 supported = (SUPPORTED_10baseT_Half |
602 SUPPORTED_10baseT_Full |
603 SUPPORTED_100baseT_Half |
604 SUPPORTED_100baseT_Full);
605
606 if (priv->flags & TSEC_GIGABIT)
607 supported |= SUPPORTED_1000baseT_Full;
wdenk78924a72004-04-18 21:45:42 +0000608
Mingkai Hue0653bf2011-01-27 12:52:46 +0800609 /* Assign a Physical address to the TBI */
Bin Meng74314f12016-01-11 22:41:25 -0800610 out_be32(&regs->tbipa, priv->tbiaddr);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800611
Andy Fleming422effd2011-04-08 02:10:54 -0500612 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
613 tsec_configure_serdes(priv);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800614
Tom Rinie8020a52022-11-27 10:25:04 -0500615#if defined(CONFIG_DM_MDIO)
Vladimir Oltean26980e92021-03-14 20:14:56 +0800616 phydev = dm_eth_phy_connect(priv->dev);
Hou Zhiqiangd35de972020-07-16 18:09:12 +0800617#else
Bin Menge86a6cd2016-01-11 22:41:22 -0800618 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
619 priv->interface);
Hou Zhiqiangd35de972020-07-16 18:09:12 +0800620#endif
Claudiu Manoilfe56fec2013-12-10 15:21:04 +0200621 if (!phydev)
622 return 0;
Mingkai Hue0653bf2011-01-27 12:52:46 +0800623
Andy Fleming422effd2011-04-08 02:10:54 -0500624 phydev->supported &= supported;
625 phydev->advertising = phydev->supported;
wdenka445ddf2004-06-09 00:34:46 +0000626
Andy Fleming422effd2011-04-08 02:10:54 -0500627 priv->phydev = phydev;
wdenk78924a72004-04-18 21:45:42 +0000628
Andy Fleming422effd2011-04-08 02:10:54 -0500629 phy_config(phydev);
Mingkai Hue0653bf2011-01-27 12:52:46 +0800630
631 return 1;
wdenk78924a72004-04-18 21:45:42 +0000632}
633
Bin Meng1048f612016-01-11 22:41:24 -0800634int tsec_probe(struct udevice *dev)
635{
Simon Glassfa20e932020-12-03 16:55:20 -0700636 struct eth_pdata *pdata = dev_get_plat(dev);
Vladimir Olteana11c89d2019-07-19 00:29:55 +0300637 struct tsec_private *priv = dev_get_priv(dev);
Mario Six00ba0552018-01-15 11:08:23 +0100638 struct ofnode_phandle_args phandle_args;
Tom Rini6a5dccc2022-11-16 13:10:41 -0500639 u32 tbiaddr = CFG_SYS_TBIPA_VALUE;
Hou Zhiqiang5966b6d2020-07-16 18:09:14 +0800640 struct tsec_data *data;
Bin Mengdbc4c2e2021-03-14 20:15:01 +0800641 ofnode parent, child;
Vladimir Oltean3095e342019-07-19 00:29:54 +0300642 fdt_addr_t reg;
Aleksandar Gerasimovski1d3c81b2021-06-04 13:40:58 +0000643 u32 max_speed;
Bin Meng1048f612016-01-11 22:41:24 -0800644 int ret;
645
Hou Zhiqiang5966b6d2020-07-16 18:09:14 +0800646 data = (struct tsec_data *)dev_get_driver_data(dev);
647
Mario Six00ba0552018-01-15 11:08:23 +0100648 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
Bin Mengdbc4c2e2021-03-14 20:15:01 +0800649 if (pdata->iobase == FDT_ADDR_T_NONE) {
650 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
651 if (strncmp(ofnode_get_name(child), "queue-group",
652 strlen("queue-group")))
653 continue;
654
655 reg = ofnode_get_addr(child);
656 if (reg == FDT_ADDR_T_NONE) {
657 printf("No 'reg' property of <queue-group>\n");
658 return -ENOENT;
659 }
660 pdata->iobase = reg;
661
662 /*
663 * if there are multiple queue groups,
664 * only the first one is used.
665 */
666 break;
667 }
668
669 if (!ofnode_valid(child)) {
670 printf("No child node for <queue-group>?\n");
671 return -ENOENT;
672 }
673 }
674
Bin Meng8699b2e2021-03-14 20:14:59 +0800675 priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
Bin Meng1048f612016-01-11 22:41:24 -0800676
Vladimir Olteand6392202019-07-19 00:29:53 +0300677 ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
678 &phandle_args);
Hou Zhiqiang53907d52020-05-03 22:48:43 +0800679 if (ret == 0) {
Vladimir Olteand6392202019-07-19 00:29:53 +0300680 ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
681
Hou Zhiqiang53907d52020-05-03 22:48:43 +0800682 parent = ofnode_get_parent(phandle_args.node);
683 if (!ofnode_valid(parent)) {
684 printf("No parent node for TBI PHY?\n");
685 return -ENOENT;
686 }
687
688 reg = ofnode_get_addr_index(parent, 0);
689 if (reg == FDT_ADDR_T_NONE) {
690 printf("No 'reg' property of MII for TBI PHY\n");
691 return -ENOENT;
692 }
693
Hou Zhiqiang5966b6d2020-07-16 18:09:14 +0800694 priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
Hou Zhiqiang53907d52020-05-03 22:48:43 +0800695 0, MAP_NOCACHE);
696 }
697
Vladimir Olteand6392202019-07-19 00:29:53 +0300698 priv->tbiaddr = tbiaddr;
Bin Meng74314f12016-01-11 22:41:25 -0800699
Marek BehĂșnbc194772022-04-07 00:33:01 +0200700 pdata->phy_interface = dev_read_phy_mode(dev);
Marek BehĂșn48631e42022-04-07 00:33:03 +0200701 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
Vladimir Oltean0e577572021-09-18 15:46:54 +0300702 pdata->phy_interface = tsec_get_interface(priv);
703
Bin Meng1048f612016-01-11 22:41:24 -0800704 priv->interface = pdata->phy_interface;
705
Aleksandar Gerasimovski1d3c81b2021-06-04 13:40:58 +0000706 /* Check for speed limit, default is 1000Mbps */
707 max_speed = dev_read_u32_default(dev, "max-speed", 1000);
708
Bin Meng1048f612016-01-11 22:41:24 -0800709 /* Initialize flags */
Aleksandar Gerasimovski1d3c81b2021-06-04 13:40:58 +0000710 if (max_speed == 1000)
711 priv->flags = TSEC_GIGABIT;
Bin Meng1048f612016-01-11 22:41:24 -0800712 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
713 priv->flags |= TSEC_SGMII;
714
Bin Meng1048f612016-01-11 22:41:24 -0800715 /* Reset the MAC */
716 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
717 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
718 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
719
720 priv->dev = dev;
721 priv->bus = miiphy_get_dev_by_name(dev->name);
722
723 /* Try to initialize PHY here, and return */
724 return !init_phy(priv);
725}
726
727int tsec_remove(struct udevice *dev)
728{
Simon Glass95588622020-12-22 19:30:28 -0700729 struct tsec_private *priv = dev_get_priv(dev);
Bin Meng1048f612016-01-11 22:41:24 -0800730
731 free(priv->phydev);
732 mdio_unregister(priv->bus);
733 mdio_free(priv->bus);
734
735 return 0;
736}
737
738static const struct eth_ops tsec_ops = {
739 .start = tsec_init,
740 .send = tsec_send,
741 .recv = tsec_recv,
742 .free_pkt = tsec_free_pkt,
743 .stop = tsec_halt,
Bin Meng1048f612016-01-11 22:41:24 -0800744 .mcast = tsec_mcast_addr,
Vladimir Oltean3556c4d2021-09-29 18:04:36 +0300745 .set_promisc = tsec_set_promisc,
Bin Meng1048f612016-01-11 22:41:24 -0800746};
747
Hou Zhiqiang5966b6d2020-07-16 18:09:14 +0800748static struct tsec_data etsec2_data = {
749 .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
750};
751
752static struct tsec_data gianfar_data = {
753 .mdio_regs_off = 0x0,
754};
755
Bin Meng1048f612016-01-11 22:41:24 -0800756static const struct udevice_id tsec_ids[] = {
Hou Zhiqiang5966b6d2020-07-16 18:09:14 +0800757 { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
758 { .compatible = "gianfar", .data = (ulong)&gianfar_data },
Bin Meng1048f612016-01-11 22:41:24 -0800759 { }
760};
761
762U_BOOT_DRIVER(eth_tsec) = {
763 .name = "tsec",
764 .id = UCLASS_ETH,
765 .of_match = tsec_ids,
766 .probe = tsec_probe,
767 .remove = tsec_remove,
768 .ops = &tsec_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700769 .priv_auto = sizeof(struct tsec_private),
Simon Glass71fa5b42020-12-03 16:55:18 -0700770 .plat_auto = sizeof(struct eth_pdata),
Bin Meng1048f612016-01-11 22:41:24 -0800771 .flags = DM_FLAG_ALLOC_PRIV_DMA,
772};