Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 2 | /* |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 3 | * Freescale Three Speed Ethernet Controller driver |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | * |
Claudiu Manoil | cd0c412 | 2013-09-30 12:44:42 +0300 | [diff] [blame] | 5 | * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 6 | * (C) Copyright 2003, Motorola, Inc. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 7 | * author Andy Fleming |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <config.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 11 | #include <common.h> |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 12 | #include <dm.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 13 | #include <malloc.h> |
| 14 | #include <net.h> |
| 15 | #include <command.h> |
Andy Fleming | c067fc1 | 2008-08-31 16:33:25 -0500 | [diff] [blame] | 16 | #include <tsec.h> |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 17 | #include <fsl_mdio.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 18 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 19 | #include <linux/delay.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 20 | #include <linux/errno.h> |
Hou Zhiqiang | d35de97 | 2020-07-16 18:09:12 +0800 | [diff] [blame] | 21 | #include <miiphy.h> |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 22 | #include <asm/processor.h> |
Alison Wang | 32cc591 | 2014-09-05 13:52:38 +0800 | [diff] [blame] | 23 | #include <asm/io.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 24 | |
Andy Fleming | ac65e07 | 2008-08-31 16:33:27 -0500 | [diff] [blame] | 25 | #define TBIANA_SETTINGS ( \ |
| 26 | TBIANA_ASYMMETRIC_PAUSE \ |
| 27 | | TBIANA_SYMMETRIC_PAUSE \ |
| 28 | | TBIANA_FULL_DUPLEX \ |
| 29 | ) |
| 30 | |
Felix Radensky | 27f98e0 | 2010-06-28 01:57:39 +0300 | [diff] [blame] | 31 | /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ |
| 32 | #ifndef CONFIG_TSEC_TBICR_SETTINGS |
Kumar Gala | c1457f9 | 2010-12-01 22:55:54 -0600 | [diff] [blame] | 33 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ |
Andy Fleming | ac65e07 | 2008-08-31 16:33:27 -0500 | [diff] [blame] | 34 | TBICR_PHY_RESET \ |
Kumar Gala | c1457f9 | 2010-12-01 22:55:54 -0600 | [diff] [blame] | 35 | | TBICR_ANEG_ENABLE \ |
Andy Fleming | ac65e07 | 2008-08-31 16:33:27 -0500 | [diff] [blame] | 36 | | TBICR_FULL_DUPLEX \ |
| 37 | | TBICR_SPEED1_SET \ |
| 38 | ) |
Felix Radensky | 27f98e0 | 2010-06-28 01:57:39 +0300 | [diff] [blame] | 39 | #endif /* CONFIG_TSEC_TBICR_SETTINGS */ |
Peter Tyser | 583c1f4 | 2009-11-03 17:52:07 -0600 | [diff] [blame] | 40 | |
Andy Fleming | ac65e07 | 2008-08-31 16:33:27 -0500 | [diff] [blame] | 41 | /* Configure the TBI for SGMII operation */ |
| 42 | static void tsec_configure_serdes(struct tsec_private *priv) |
| 43 | { |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 44 | /* |
| 45 | * Access TBI PHY registers at given TSEC register offset as opposed |
| 46 | * to the register offset used for external PHY accesses |
| 47 | */ |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 48 | tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 49 | 0, TBI_ANA, TBIANA_SETTINGS); |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 50 | tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 51 | 0, TBI_TBICON, TBICON_CLK_SELECT); |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 52 | tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 53 | 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS); |
David Updegraff | 0451b01 | 2007-04-20 14:34:48 -0500 | [diff] [blame] | 54 | } |
| 55 | |
Chris Packham | bbe1857 | 2018-11-26 21:00:28 +1300 | [diff] [blame] | 56 | /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c |
| 57 | * and this is the ethernet-crc method needed for TSEC -- and perhaps |
| 58 | * some other adapter -- hash tables |
| 59 | */ |
| 60 | #define CRCPOLY_LE 0xedb88320 |
| 61 | static u32 ether_crc(size_t len, unsigned char const *p) |
| 62 | { |
| 63 | int i; |
| 64 | u32 crc; |
| 65 | |
| 66 | crc = ~0; |
| 67 | while (len--) { |
| 68 | crc ^= *p++; |
| 69 | for (i = 0; i < 8; i++) |
| 70 | crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); |
| 71 | } |
| 72 | /* an reverse the bits, cuz of way they arrive -- last-first */ |
| 73 | crc = (crc >> 16) | (crc << 16); |
| 74 | crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); |
| 75 | crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); |
| 76 | crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); |
| 77 | crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); |
| 78 | return crc; |
| 79 | } |
| 80 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 81 | /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ |
| 82 | |
| 83 | /* Set the appropriate hash bit for the given addr */ |
| 84 | |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 85 | /* |
| 86 | * The algorithm works like so: |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 87 | * 1) Take the Destination Address (ie the multicast address), and |
| 88 | * do a CRC on it (little endian), and reverse the bits of the |
| 89 | * result. |
| 90 | * 2) Use the 8 most significant bits as a hash into a 256-entry |
| 91 | * table. The table is controlled through 8 32-bit registers: |
Claudiu Manoil | 461511b | 2013-09-30 12:44:40 +0300 | [diff] [blame] | 92 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry |
| 93 | * 255. This means that the 3 most significant bits in the |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 94 | * hash index which gaddr register to use, and the 5 other bits |
| 95 | * indicate which bit (assuming an IBM numbering scheme, which |
Claudiu Manoil | 461511b | 2013-09-30 12:44:40 +0300 | [diff] [blame] | 96 | * for PowerPC (tm) is usually the case) in the register holds |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 97 | * the entry. |
| 98 | */ |
Chris Packham | a55ef7f | 2018-11-26 21:00:29 +1300 | [diff] [blame] | 99 | static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join) |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 100 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 101 | struct tsec_private *priv; |
| 102 | struct tsec __iomem *regs; |
Claudiu Manoil | 461511b | 2013-09-30 12:44:40 +0300 | [diff] [blame] | 103 | u32 result, value; |
| 104 | u8 whichbit, whichreg; |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 105 | |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 106 | priv = dev_get_priv(dev); |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 107 | regs = priv->regs; |
Claudiu Manoil | 461511b | 2013-09-30 12:44:40 +0300 | [diff] [blame] | 108 | result = ether_crc(MAC_ADDR_LEN, mcast_mac); |
| 109 | whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */ |
| 110 | whichreg = result >> 29; /* the 3 MSB = which reg to set it in */ |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 111 | |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 112 | value = BIT(31 - whichbit); |
Claudiu Manoil | 461511b | 2013-09-30 12:44:40 +0300 | [diff] [blame] | 113 | |
Chris Packham | a55ef7f | 2018-11-26 21:00:29 +1300 | [diff] [blame] | 114 | if (join) |
Claudiu Manoil | 461511b | 2013-09-30 12:44:40 +0300 | [diff] [blame] | 115 | setbits_be32(®s->hash.gaddr0 + whichreg, value); |
| 116 | else |
| 117 | clrbits_be32(®s->hash.gaddr0 + whichreg, value); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 118 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 119 | return 0; |
| 120 | } |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 121 | |
Tom Rini | 5c1b071 | 2022-12-13 09:26:25 -0500 | [diff] [blame] | 122 | static int tsec_set_promisc(struct udevice *dev, bool enable) |
Vladimir Oltean | 3556c4d | 2021-09-29 18:04:36 +0300 | [diff] [blame] | 123 | { |
| 124 | struct tsec_private *priv = dev_get_priv(dev); |
| 125 | struct tsec __iomem *regs = priv->regs; |
| 126 | |
| 127 | if (enable) |
| 128 | setbits_be32(®s->rctrl, RCTRL_PROM); |
| 129 | else |
| 130 | clrbits_be32(®s->rctrl, RCTRL_PROM); |
| 131 | |
| 132 | return 0; |
| 133 | } |
| 134 | |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 135 | /* |
| 136 | * Initialized required registers to appropriate values, zeroing |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 137 | * those we don't care about (unless zero is bad, in which case, |
| 138 | * choose a more appropriate value) |
| 139 | */ |
Claudiu Manoil | cd0c412 | 2013-09-30 12:44:42 +0300 | [diff] [blame] | 140 | static void init_registers(struct tsec __iomem *regs) |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 141 | { |
| 142 | /* Clear IEVENT */ |
| 143 | out_be32(®s->ievent, IEVENT_INIT_CLEAR); |
| 144 | |
| 145 | out_be32(®s->imask, IMASK_INIT_CLEAR); |
| 146 | |
| 147 | out_be32(®s->hash.iaddr0, 0); |
| 148 | out_be32(®s->hash.iaddr1, 0); |
| 149 | out_be32(®s->hash.iaddr2, 0); |
| 150 | out_be32(®s->hash.iaddr3, 0); |
| 151 | out_be32(®s->hash.iaddr4, 0); |
| 152 | out_be32(®s->hash.iaddr5, 0); |
| 153 | out_be32(®s->hash.iaddr6, 0); |
| 154 | out_be32(®s->hash.iaddr7, 0); |
| 155 | |
| 156 | out_be32(®s->hash.gaddr0, 0); |
| 157 | out_be32(®s->hash.gaddr1, 0); |
| 158 | out_be32(®s->hash.gaddr2, 0); |
| 159 | out_be32(®s->hash.gaddr3, 0); |
| 160 | out_be32(®s->hash.gaddr4, 0); |
| 161 | out_be32(®s->hash.gaddr5, 0); |
| 162 | out_be32(®s->hash.gaddr6, 0); |
| 163 | out_be32(®s->hash.gaddr7, 0); |
| 164 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 165 | /* Init RMON mib registers */ |
Claudiu Manoil | a18ab90 | 2013-09-30 12:44:46 +0300 | [diff] [blame] | 166 | memset((void *)®s->rmon, 0, sizeof(regs->rmon)); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 167 | |
| 168 | out_be32(®s->rmon.cam1, 0xffffffff); |
| 169 | out_be32(®s->rmon.cam2, 0xffffffff); |
| 170 | |
| 171 | out_be32(®s->mrblr, MRBLR_INIT_SETTINGS); |
| 172 | |
| 173 | out_be32(®s->minflr, MINFLR_INIT_SETTINGS); |
| 174 | |
| 175 | out_be32(®s->attr, ATTR_INIT_SETTINGS); |
| 176 | out_be32(®s->attreli, ATTRELI_INIT_SETTINGS); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 177 | } |
| 178 | |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 179 | /* |
| 180 | * Configure maccfg2 based on negotiated speed and duplex |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 181 | * reported by PHY handling code |
| 182 | */ |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 183 | static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 184 | { |
Claudiu Manoil | cd0c412 | 2013-09-30 12:44:42 +0300 | [diff] [blame] | 185 | struct tsec __iomem *regs = priv->regs; |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 186 | u32 ecntrl, maccfg2; |
| 187 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 188 | if (!phydev->link) { |
| 189 | printf("%s: No link.\n", phydev->dev->name); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 190 | return; |
| 191 | } |
| 192 | |
| 193 | /* clear all bits relative with interface mode */ |
| 194 | ecntrl = in_be32(®s->ecntrl); |
| 195 | ecntrl &= ~ECNTRL_R100; |
| 196 | |
| 197 | maccfg2 = in_be32(®s->maccfg2); |
| 198 | maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX); |
| 199 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 200 | if (phydev->duplex) |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 201 | maccfg2 |= MACCFG2_FULL_DUPLEX; |
| 202 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 203 | switch (phydev->speed) { |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 204 | case 1000: |
| 205 | maccfg2 |= MACCFG2_GMII; |
| 206 | break; |
| 207 | case 100: |
| 208 | case 10: |
| 209 | maccfg2 |= MACCFG2_MII; |
| 210 | |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 211 | /* |
| 212 | * Set R100 bit in all modes although |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 213 | * it is only used in RGMII mode |
| 214 | */ |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 215 | if (phydev->speed == 100) |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 216 | ecntrl |= ECNTRL_R100; |
| 217 | break; |
| 218 | default: |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 219 | printf("%s: Speed was bad\n", phydev->dev->name); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 220 | break; |
| 221 | } |
| 222 | |
| 223 | out_be32(®s->ecntrl, ecntrl); |
| 224 | out_be32(®s->maccfg2, maccfg2); |
wdenk | f41ff3b | 2005-04-04 23:43:44 +0000 | [diff] [blame] | 225 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 226 | printf("Speed: %d, %s duplex%s\n", phydev->speed, |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 227 | (phydev->duplex) ? "full" : "half", |
| 228 | (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 229 | } |
wdenk | bfad55d | 2005-03-14 23:56:42 +0000 | [diff] [blame] | 230 | |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 231 | /* |
| 232 | * This returns the status bits of the device. The return value |
| 233 | * is never checked, and this is what the 8260 driver did, so we |
| 234 | * do the same. Presumably, this would be zero if there were no |
| 235 | * errors |
| 236 | */ |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 237 | static int tsec_send(struct udevice *dev, void *packet, int length) |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 238 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 239 | struct tsec_private *priv; |
| 240 | struct tsec __iomem *regs; |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 241 | int result = 0; |
Vladimir Oltean | a11c89d | 2019-07-19 00:29:55 +0300 | [diff] [blame] | 242 | u16 status; |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 243 | int i; |
| 244 | |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 245 | priv = dev_get_priv(dev); |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 246 | regs = priv->regs; |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 247 | /* Find an empty buffer descriptor */ |
| 248 | for (i = 0; |
| 249 | in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY; |
| 250 | i++) { |
| 251 | if (i >= TOUT_LOOP) { |
Vladimir Oltean | 8ec8eaa | 2019-07-19 00:29:56 +0300 | [diff] [blame] | 252 | printf("%s: tsec: tx buffers full\n", dev->name); |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 253 | return result; |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet); |
| 258 | out_be16(&priv->txbd[priv->tx_idx].length, length); |
| 259 | status = in_be16(&priv->txbd[priv->tx_idx].status); |
| 260 | out_be16(&priv->txbd[priv->tx_idx].status, status | |
| 261 | (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); |
| 262 | |
| 263 | /* Tell the DMA to go */ |
| 264 | out_be32(®s->tstat, TSTAT_CLEAR_THALT); |
| 265 | |
| 266 | /* Wait for buffer to be transmitted */ |
| 267 | for (i = 0; |
| 268 | in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY; |
| 269 | i++) { |
| 270 | if (i >= TOUT_LOOP) { |
Vladimir Oltean | 8ec8eaa | 2019-07-19 00:29:56 +0300 | [diff] [blame] | 271 | printf("%s: tsec: tx error\n", dev->name); |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 272 | return result; |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT; |
| 277 | result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS; |
| 278 | |
| 279 | return result; |
| 280 | } |
| 281 | |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 282 | static int tsec_recv(struct udevice *dev, int flags, uchar **packetp) |
| 283 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 284 | struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev); |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 285 | struct tsec __iomem *regs = priv->regs; |
| 286 | int ret = -1; |
| 287 | |
| 288 | if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) { |
| 289 | int length = in_be16(&priv->rxbd[priv->rx_idx].length); |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 290 | u16 status = in_be16(&priv->rxbd[priv->rx_idx].status); |
| 291 | u32 buf; |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 292 | |
| 293 | /* Send the packet up if there were no errors */ |
| 294 | if (!(status & RXBD_STATS)) { |
| 295 | buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr); |
| 296 | *packetp = (uchar *)buf; |
| 297 | ret = length - 4; |
| 298 | } else { |
| 299 | printf("Got error %x\n", (status & RXBD_STATS)); |
| 300 | } |
| 301 | } |
| 302 | |
| 303 | if (in_be32(®s->ievent) & IEVENT_BSY) { |
| 304 | out_be32(®s->ievent, IEVENT_BSY); |
| 305 | out_be32(®s->rstat, RSTAT_CLEAR_RHALT); |
| 306 | } |
| 307 | |
| 308 | return ret; |
| 309 | } |
| 310 | |
| 311 | static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length) |
| 312 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 313 | struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev); |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 314 | u16 status; |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 315 | |
| 316 | out_be16(&priv->rxbd[priv->rx_idx].length, 0); |
| 317 | |
| 318 | status = RXBD_EMPTY; |
| 319 | /* Set the wrap bit if this is the last element in the list */ |
| 320 | if ((priv->rx_idx + 1) == PKTBUFSRX) |
| 321 | status |= RXBD_WRAP; |
| 322 | out_be16(&priv->rxbd[priv->rx_idx].status, status); |
| 323 | |
| 324 | priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; |
| 325 | |
| 326 | return 0; |
| 327 | } |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 328 | |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 329 | static void tsec_halt(struct udevice *dev) |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 330 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 331 | struct tsec_private *priv; |
| 332 | struct tsec __iomem *regs; |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 333 | priv = dev_get_priv(dev); |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 334 | regs = priv->regs; |
Bin Meng | 80b1a1c | 2016-01-11 22:41:21 -0800 | [diff] [blame] | 335 | |
| 336 | clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
| 337 | setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
| 338 | |
| 339 | while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) |
| 340 | != (IEVENT_GRSC | IEVENT_GTSC)) |
| 341 | ; |
| 342 | |
| 343 | clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); |
| 344 | |
| 345 | /* Shut down the PHY, as needed */ |
| 346 | phy_shutdown(priv->phydev); |
| 347 | } |
| 348 | |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 349 | #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
| 350 | /* |
| 351 | * When MACCFG1[Rx_EN] is enabled during system boot as part |
| 352 | * of the eTSEC port initialization sequence, |
| 353 | * the eTSEC Rx logic may not be properly initialized. |
| 354 | */ |
Bin Meng | 1886407 | 2021-11-01 14:15:12 +0800 | [diff] [blame] | 355 | static void redundant_init(struct tsec_private *priv) |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 356 | { |
Claudiu Manoil | cd0c412 | 2013-09-30 12:44:42 +0300 | [diff] [blame] | 357 | struct tsec __iomem *regs = priv->regs; |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 358 | uint t, count = 0; |
| 359 | int fail = 1; |
| 360 | static const u8 pkt[] = { |
| 361 | 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25, |
| 362 | 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00, |
| 363 | 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01, |
| 364 | 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1, |
| 365 | 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00, |
| 366 | 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, |
| 367 | 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, |
| 368 | 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, |
| 369 | 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, |
| 370 | 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, |
| 371 | 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, |
| 372 | 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, |
| 373 | 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, |
| 374 | 0x71, 0x72}; |
| 375 | |
| 376 | /* Enable promiscuous mode */ |
Vladimir Oltean | 3556c4d | 2021-09-29 18:04:36 +0300 | [diff] [blame] | 377 | setbits_be32(®s->rctrl, RCTRL_PROM); |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 378 | /* Enable loopback mode */ |
| 379 | setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); |
| 380 | /* Enable transmit and receive */ |
| 381 | setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); |
| 382 | |
| 383 | /* Tell the DMA it is clear to go */ |
| 384 | setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); |
| 385 | out_be32(®s->tstat, TSTAT_CLEAR_THALT); |
| 386 | out_be32(®s->rstat, RSTAT_CLEAR_RHALT); |
| 387 | clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
| 388 | |
| 389 | do { |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 390 | u16 status; |
| 391 | |
Bin Meng | e86a6cd | 2016-01-11 22:41:22 -0800 | [diff] [blame] | 392 | tsec_send(priv->dev, (void *)pkt, sizeof(pkt)); |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 393 | |
| 394 | /* Wait for buffer to be received */ |
Bin Meng | 1120c54 | 2016-01-11 22:41:20 -0800 | [diff] [blame] | 395 | for (t = 0; |
| 396 | in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY; |
Bin Meng | 76f5399 | 2016-01-11 22:41:19 -0800 | [diff] [blame] | 397 | t++) { |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 398 | if (t >= 10 * TOUT_LOOP) { |
Bin Meng | e86a6cd | 2016-01-11 22:41:22 -0800 | [diff] [blame] | 399 | printf("%s: tsec: rx error\n", priv->dev->name); |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 400 | break; |
| 401 | } |
| 402 | } |
| 403 | |
Bin Meng | 76f5399 | 2016-01-11 22:41:19 -0800 | [diff] [blame] | 404 | if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt))) |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 405 | fail = 0; |
| 406 | |
Bin Meng | 1120c54 | 2016-01-11 22:41:20 -0800 | [diff] [blame] | 407 | out_be16(&priv->rxbd[priv->rx_idx].length, 0); |
Claudiu Manoil | eec416b | 2013-10-04 19:13:53 +0300 | [diff] [blame] | 408 | status = RXBD_EMPTY; |
Bin Meng | 76f5399 | 2016-01-11 22:41:19 -0800 | [diff] [blame] | 409 | if ((priv->rx_idx + 1) == PKTBUFSRX) |
Claudiu Manoil | eec416b | 2013-10-04 19:13:53 +0300 | [diff] [blame] | 410 | status |= RXBD_WRAP; |
Bin Meng | 1120c54 | 2016-01-11 22:41:20 -0800 | [diff] [blame] | 411 | out_be16(&priv->rxbd[priv->rx_idx].status, status); |
Bin Meng | 76f5399 | 2016-01-11 22:41:19 -0800 | [diff] [blame] | 412 | priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 413 | |
| 414 | if (in_be32(®s->ievent) & IEVENT_BSY) { |
| 415 | out_be32(®s->ievent, IEVENT_BSY); |
| 416 | out_be32(®s->rstat, RSTAT_CLEAR_RHALT); |
| 417 | } |
| 418 | if (fail) { |
| 419 | printf("loopback recv packet error!\n"); |
| 420 | clrbits_be32(®s->maccfg1, MACCFG1_RX_EN); |
| 421 | udelay(1000); |
| 422 | setbits_be32(®s->maccfg1, MACCFG1_RX_EN); |
| 423 | } |
| 424 | } while ((count++ < 4) && (fail == 1)); |
| 425 | |
| 426 | if (fail) |
| 427 | panic("eTSEC init fail!\n"); |
| 428 | /* Disable promiscuous mode */ |
Vladimir Oltean | 3556c4d | 2021-09-29 18:04:36 +0300 | [diff] [blame] | 429 | clrbits_be32(®s->rctrl, RCTRL_PROM); |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 430 | /* Disable loopback mode */ |
| 431 | clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); |
| 432 | } |
| 433 | #endif |
| 434 | |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 435 | /* |
| 436 | * Set up the buffers and their descriptors, and bring up the |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 437 | * interface |
Jon Loeliger | b7ced08 | 2006-10-10 17:03:43 -0500 | [diff] [blame] | 438 | */ |
Bin Meng | e86a6cd | 2016-01-11 22:41:22 -0800 | [diff] [blame] | 439 | static void startup_tsec(struct tsec_private *priv) |
Wolfgang Denk | f0c4e46 | 2006-03-12 22:50:55 +0100 | [diff] [blame] | 440 | { |
Claudiu Manoil | cd0c412 | 2013-09-30 12:44:42 +0300 | [diff] [blame] | 441 | struct tsec __iomem *regs = priv->regs; |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 442 | u16 status; |
Claudiu Manoil | eec416b | 2013-10-04 19:13:53 +0300 | [diff] [blame] | 443 | int i; |
Wolfgang Denk | f0c4e46 | 2006-03-12 22:50:55 +0100 | [diff] [blame] | 444 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 445 | /* reset the indices to zero */ |
Bin Meng | 76f5399 | 2016-01-11 22:41:19 -0800 | [diff] [blame] | 446 | priv->rx_idx = 0; |
| 447 | priv->tx_idx = 0; |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 448 | #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
| 449 | uint svr; |
| 450 | #endif |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 451 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 452 | /* Point to the buffer descriptors */ |
Bin Meng | 1120c54 | 2016-01-11 22:41:20 -0800 | [diff] [blame] | 453 | out_be32(®s->tbase, (u32)&priv->txbd[0]); |
| 454 | out_be32(®s->rbase, (u32)&priv->rxbd[0]); |
Wolfgang Denk | f0c4e46 | 2006-03-12 22:50:55 +0100 | [diff] [blame] | 455 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 456 | /* Initialize the Rx Buffer descriptors */ |
| 457 | for (i = 0; i < PKTBUFSRX; i++) { |
Bin Meng | 1120c54 | 2016-01-11 22:41:20 -0800 | [diff] [blame] | 458 | out_be16(&priv->rxbd[i].status, RXBD_EMPTY); |
| 459 | out_be16(&priv->rxbd[i].length, 0); |
| 460 | out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 461 | } |
Bin Meng | 1120c54 | 2016-01-11 22:41:20 -0800 | [diff] [blame] | 462 | status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status); |
| 463 | out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); |
Wolfgang Denk | f0c4e46 | 2006-03-12 22:50:55 +0100 | [diff] [blame] | 464 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 465 | /* Initialize the TX Buffer Descriptors */ |
| 466 | for (i = 0; i < TX_BUF_CNT; i++) { |
Bin Meng | 1120c54 | 2016-01-11 22:41:20 -0800 | [diff] [blame] | 467 | out_be16(&priv->txbd[i].status, 0); |
| 468 | out_be16(&priv->txbd[i].length, 0); |
| 469 | out_be32(&priv->txbd[i].bufptr, 0); |
Wolfgang Denk | f0c4e46 | 2006-03-12 22:50:55 +0100 | [diff] [blame] | 470 | } |
Bin Meng | 1120c54 | 2016-01-11 22:41:20 -0800 | [diff] [blame] | 471 | status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status); |
| 472 | out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); |
Wolfgang Denk | f0c4e46 | 2006-03-12 22:50:55 +0100 | [diff] [blame] | 473 | |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 474 | #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
| 475 | svr = get_svr(); |
| 476 | if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) |
Bin Meng | e86a6cd | 2016-01-11 22:41:22 -0800 | [diff] [blame] | 477 | redundant_init(priv); |
chenhui zhao | c8caa8a | 2011-10-03 08:38:50 -0500 | [diff] [blame] | 478 | #endif |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 479 | /* Enable Transmit and Receive */ |
| 480 | setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); |
| 481 | |
| 482 | /* Tell the DMA it is clear to go */ |
| 483 | setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); |
| 484 | out_be32(®s->tstat, TSTAT_CLEAR_THALT); |
| 485 | out_be32(®s->rstat, RSTAT_CLEAR_RHALT); |
| 486 | clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
Wolfgang Denk | f0c4e46 | 2006-03-12 22:50:55 +0100 | [diff] [blame] | 487 | } |
| 488 | |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 489 | /* |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 490 | * Initializes data structures and registers for the controller, |
| 491 | * and brings the interface up. Returns the link status, meaning |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 492 | * that it returns success if the link is up, failure otherwise. |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 493 | * This allows U-Boot to find the first active controller. |
Jon Loeliger | b7ced08 | 2006-10-10 17:03:43 -0500 | [diff] [blame] | 494 | */ |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 495 | static int tsec_init(struct udevice *dev) |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 496 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 497 | struct tsec_private *priv; |
| 498 | struct tsec __iomem *regs; |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 499 | struct eth_pdata *pdata = dev_get_plat(dev); |
Claudiu Manoil | dcb38fe | 2013-09-30 12:44:47 +0300 | [diff] [blame] | 500 | u32 tempval; |
Timur Tabi | 4238746 | 2012-07-09 08:52:43 +0000 | [diff] [blame] | 501 | int ret; |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 502 | |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 503 | priv = dev_get_priv(dev); |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 504 | regs = priv->regs; |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 505 | /* Make sure the controller is stopped */ |
| 506 | tsec_halt(dev); |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 507 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 508 | /* Init MACCFG2. Defaults to GMII */ |
| 509 | out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS); |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 510 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 511 | /* Init ECNTRL */ |
| 512 | out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 513 | |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 514 | /* |
| 515 | * Copy the station address into the address registers. |
Claudiu Manoil | dcb38fe | 2013-09-30 12:44:47 +0300 | [diff] [blame] | 516 | * For a station address of 0x12345678ABCD in transmission |
| 517 | * order (BE), MACnADDR1 is set to 0xCDAB7856 and |
| 518 | * MACnADDR2 is set to 0x34120000. |
| 519 | */ |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 520 | tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) | |
| 521 | (pdata->enetaddr[3] << 8) | pdata->enetaddr[2]; |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 522 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 523 | out_be32(®s->macstnaddr1, tempval); |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 524 | |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 525 | tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16); |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 526 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 527 | out_be32(®s->macstnaddr2, tempval); |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 528 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 529 | /* Clear out (for the most part) the other registers */ |
| 530 | init_registers(regs); |
| 531 | |
| 532 | /* Ready the device for tx/rx */ |
Bin Meng | e86a6cd | 2016-01-11 22:41:22 -0800 | [diff] [blame] | 533 | startup_tsec(priv); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 534 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 535 | /* Start up the PHY */ |
Timur Tabi | 4238746 | 2012-07-09 08:52:43 +0000 | [diff] [blame] | 536 | ret = phy_startup(priv->phydev); |
| 537 | if (ret) { |
| 538 | printf("Could not initialize PHY %s\n", |
| 539 | priv->phydev->dev->name); |
| 540 | return ret; |
| 541 | } |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 542 | |
| 543 | adjust_link(priv, priv->phydev); |
| 544 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 545 | /* If there's no link, fail */ |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 546 | return priv->phydev->link ? 0 : -1; |
| 547 | } |
| 548 | |
Ramon Fried | 8ca1e6b | 2021-09-28 18:49:02 +0300 | [diff] [blame] | 549 | static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv) |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 550 | { |
Claudiu Manoil | cd0c412 | 2013-09-30 12:44:42 +0300 | [diff] [blame] | 551 | struct tsec __iomem *regs = priv->regs; |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 552 | u32 ecntrl; |
| 553 | |
| 554 | ecntrl = in_be32(®s->ecntrl); |
| 555 | |
| 556 | if (ecntrl & ECNTRL_SGMII_MODE) |
| 557 | return PHY_INTERFACE_MODE_SGMII; |
| 558 | |
| 559 | if (ecntrl & ECNTRL_TBI_MODE) { |
| 560 | if (ecntrl & ECNTRL_REDUCED_MODE) |
| 561 | return PHY_INTERFACE_MODE_RTBI; |
| 562 | else |
| 563 | return PHY_INTERFACE_MODE_TBI; |
| 564 | } |
| 565 | |
| 566 | if (ecntrl & ECNTRL_REDUCED_MODE) { |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 567 | phy_interface_t interface; |
| 568 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 569 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) |
| 570 | return PHY_INTERFACE_MODE_RMII; |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 571 | |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 572 | interface = priv->interface; |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 573 | |
Mario Six | c29fcc7 | 2018-01-15 11:08:21 +0100 | [diff] [blame] | 574 | /* |
| 575 | * This isn't autodetected, so it must |
| 576 | * be set by the platform code. |
| 577 | */ |
| 578 | if (interface == PHY_INTERFACE_MODE_RGMII_ID || |
| 579 | interface == PHY_INTERFACE_MODE_RGMII_TXID || |
| 580 | interface == PHY_INTERFACE_MODE_RGMII_RXID) |
| 581 | return interface; |
| 582 | |
| 583 | return PHY_INTERFACE_MODE_RGMII; |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 584 | } |
| 585 | |
| 586 | if (priv->flags & TSEC_GIGABIT) |
| 587 | return PHY_INTERFACE_MODE_GMII; |
| 588 | |
| 589 | return PHY_INTERFACE_MODE_MII; |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 590 | } |
| 591 | |
Bin Meng | 79cd33a | 2016-01-11 22:41:18 -0800 | [diff] [blame] | 592 | /* |
| 593 | * Discover which PHY is attached to the device, and configure it |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 594 | * properly. If the PHY is not recognized, then return 0 |
| 595 | * (failure). Otherwise, return 1 |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 596 | */ |
Bin Meng | e86a6cd | 2016-01-11 22:41:22 -0800 | [diff] [blame] | 597 | static int init_phy(struct tsec_private *priv) |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 598 | { |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 599 | struct phy_device *phydev; |
Claudiu Manoil | cd0c412 | 2013-09-30 12:44:42 +0300 | [diff] [blame] | 600 | struct tsec __iomem *regs = priv->regs; |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 601 | u32 supported = (SUPPORTED_10baseT_Half | |
| 602 | SUPPORTED_10baseT_Full | |
| 603 | SUPPORTED_100baseT_Half | |
| 604 | SUPPORTED_100baseT_Full); |
| 605 | |
| 606 | if (priv->flags & TSEC_GIGABIT) |
| 607 | supported |= SUPPORTED_1000baseT_Full; |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 608 | |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 609 | /* Assign a Physical address to the TBI */ |
Bin Meng | 74314f1 | 2016-01-11 22:41:25 -0800 | [diff] [blame] | 610 | out_be32(®s->tbipa, priv->tbiaddr); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 611 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 612 | if (priv->interface == PHY_INTERFACE_MODE_SGMII) |
| 613 | tsec_configure_serdes(priv); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 614 | |
Tom Rini | e8020a5 | 2022-11-27 10:25:04 -0500 | [diff] [blame] | 615 | #if defined(CONFIG_DM_MDIO) |
Vladimir Oltean | 26980e9 | 2021-03-14 20:14:56 +0800 | [diff] [blame] | 616 | phydev = dm_eth_phy_connect(priv->dev); |
Hou Zhiqiang | d35de97 | 2020-07-16 18:09:12 +0800 | [diff] [blame] | 617 | #else |
Bin Meng | e86a6cd | 2016-01-11 22:41:22 -0800 | [diff] [blame] | 618 | phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, |
| 619 | priv->interface); |
Hou Zhiqiang | d35de97 | 2020-07-16 18:09:12 +0800 | [diff] [blame] | 620 | #endif |
Claudiu Manoil | fe56fec | 2013-12-10 15:21:04 +0200 | [diff] [blame] | 621 | if (!phydev) |
| 622 | return 0; |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 623 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 624 | phydev->supported &= supported; |
| 625 | phydev->advertising = phydev->supported; |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 626 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 627 | priv->phydev = phydev; |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 628 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 629 | phy_config(phydev); |
Mingkai Hu | e0653bf | 2011-01-27 12:52:46 +0800 | [diff] [blame] | 630 | |
| 631 | return 1; |
wdenk | 78924a7 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 632 | } |
| 633 | |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 634 | int tsec_probe(struct udevice *dev) |
| 635 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 636 | struct eth_pdata *pdata = dev_get_plat(dev); |
Vladimir Oltean | a11c89d | 2019-07-19 00:29:55 +0300 | [diff] [blame] | 637 | struct tsec_private *priv = dev_get_priv(dev); |
Mario Six | 00ba055 | 2018-01-15 11:08:23 +0100 | [diff] [blame] | 638 | struct ofnode_phandle_args phandle_args; |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 639 | u32 tbiaddr = CFG_SYS_TBIPA_VALUE; |
Hou Zhiqiang | 5966b6d | 2020-07-16 18:09:14 +0800 | [diff] [blame] | 640 | struct tsec_data *data; |
Bin Meng | dbc4c2e | 2021-03-14 20:15:01 +0800 | [diff] [blame] | 641 | ofnode parent, child; |
Vladimir Oltean | 3095e34 | 2019-07-19 00:29:54 +0300 | [diff] [blame] | 642 | fdt_addr_t reg; |
Aleksandar Gerasimovski | 1d3c81b | 2021-06-04 13:40:58 +0000 | [diff] [blame] | 643 | u32 max_speed; |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 644 | int ret; |
| 645 | |
Hou Zhiqiang | 5966b6d | 2020-07-16 18:09:14 +0800 | [diff] [blame] | 646 | data = (struct tsec_data *)dev_get_driver_data(dev); |
| 647 | |
Mario Six | 00ba055 | 2018-01-15 11:08:23 +0100 | [diff] [blame] | 648 | pdata->iobase = (phys_addr_t)dev_read_addr(dev); |
Bin Meng | dbc4c2e | 2021-03-14 20:15:01 +0800 | [diff] [blame] | 649 | if (pdata->iobase == FDT_ADDR_T_NONE) { |
| 650 | ofnode_for_each_subnode(child, dev_ofnode(dev)) { |
| 651 | if (strncmp(ofnode_get_name(child), "queue-group", |
| 652 | strlen("queue-group"))) |
| 653 | continue; |
| 654 | |
| 655 | reg = ofnode_get_addr(child); |
| 656 | if (reg == FDT_ADDR_T_NONE) { |
| 657 | printf("No 'reg' property of <queue-group>\n"); |
| 658 | return -ENOENT; |
| 659 | } |
| 660 | pdata->iobase = reg; |
| 661 | |
| 662 | /* |
| 663 | * if there are multiple queue groups, |
| 664 | * only the first one is used. |
| 665 | */ |
| 666 | break; |
| 667 | } |
| 668 | |
| 669 | if (!ofnode_valid(child)) { |
| 670 | printf("No child node for <queue-group>?\n"); |
| 671 | return -ENOENT; |
| 672 | } |
| 673 | } |
| 674 | |
Bin Meng | 8699b2e | 2021-03-14 20:14:59 +0800 | [diff] [blame] | 675 | priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE); |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 676 | |
Vladimir Oltean | d639220 | 2019-07-19 00:29:53 +0300 | [diff] [blame] | 677 | ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0, |
| 678 | &phandle_args); |
Hou Zhiqiang | 53907d5 | 2020-05-03 22:48:43 +0800 | [diff] [blame] | 679 | if (ret == 0) { |
Vladimir Oltean | d639220 | 2019-07-19 00:29:53 +0300 | [diff] [blame] | 680 | ofnode_read_u32(phandle_args.node, "reg", &tbiaddr); |
| 681 | |
Hou Zhiqiang | 53907d5 | 2020-05-03 22:48:43 +0800 | [diff] [blame] | 682 | parent = ofnode_get_parent(phandle_args.node); |
| 683 | if (!ofnode_valid(parent)) { |
| 684 | printf("No parent node for TBI PHY?\n"); |
| 685 | return -ENOENT; |
| 686 | } |
| 687 | |
| 688 | reg = ofnode_get_addr_index(parent, 0); |
| 689 | if (reg == FDT_ADDR_T_NONE) { |
| 690 | printf("No 'reg' property of MII for TBI PHY\n"); |
| 691 | return -ENOENT; |
| 692 | } |
| 693 | |
Hou Zhiqiang | 5966b6d | 2020-07-16 18:09:14 +0800 | [diff] [blame] | 694 | priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off, |
Hou Zhiqiang | 53907d5 | 2020-05-03 22:48:43 +0800 | [diff] [blame] | 695 | 0, MAP_NOCACHE); |
| 696 | } |
| 697 | |
Vladimir Oltean | d639220 | 2019-07-19 00:29:53 +0300 | [diff] [blame] | 698 | priv->tbiaddr = tbiaddr; |
Bin Meng | 74314f1 | 2016-01-11 22:41:25 -0800 | [diff] [blame] | 699 | |
Marek BehĂșn | bc19477 | 2022-04-07 00:33:01 +0200 | [diff] [blame] | 700 | pdata->phy_interface = dev_read_phy_mode(dev); |
Marek BehĂșn | 48631e4 | 2022-04-07 00:33:03 +0200 | [diff] [blame] | 701 | if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) |
Vladimir Oltean | 0e57757 | 2021-09-18 15:46:54 +0300 | [diff] [blame] | 702 | pdata->phy_interface = tsec_get_interface(priv); |
| 703 | |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 704 | priv->interface = pdata->phy_interface; |
| 705 | |
Aleksandar Gerasimovski | 1d3c81b | 2021-06-04 13:40:58 +0000 | [diff] [blame] | 706 | /* Check for speed limit, default is 1000Mbps */ |
| 707 | max_speed = dev_read_u32_default(dev, "max-speed", 1000); |
| 708 | |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 709 | /* Initialize flags */ |
Aleksandar Gerasimovski | 1d3c81b | 2021-06-04 13:40:58 +0000 | [diff] [blame] | 710 | if (max_speed == 1000) |
| 711 | priv->flags = TSEC_GIGABIT; |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 712 | if (priv->interface == PHY_INTERFACE_MODE_SGMII) |
| 713 | priv->flags |= TSEC_SGMII; |
| 714 | |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 715 | /* Reset the MAC */ |
| 716 | setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); |
| 717 | udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ |
| 718 | clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); |
| 719 | |
| 720 | priv->dev = dev; |
| 721 | priv->bus = miiphy_get_dev_by_name(dev->name); |
| 722 | |
| 723 | /* Try to initialize PHY here, and return */ |
| 724 | return !init_phy(priv); |
| 725 | } |
| 726 | |
| 727 | int tsec_remove(struct udevice *dev) |
| 728 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 729 | struct tsec_private *priv = dev_get_priv(dev); |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 730 | |
| 731 | free(priv->phydev); |
| 732 | mdio_unregister(priv->bus); |
| 733 | mdio_free(priv->bus); |
| 734 | |
| 735 | return 0; |
| 736 | } |
| 737 | |
| 738 | static const struct eth_ops tsec_ops = { |
| 739 | .start = tsec_init, |
| 740 | .send = tsec_send, |
| 741 | .recv = tsec_recv, |
| 742 | .free_pkt = tsec_free_pkt, |
| 743 | .stop = tsec_halt, |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 744 | .mcast = tsec_mcast_addr, |
Vladimir Oltean | 3556c4d | 2021-09-29 18:04:36 +0300 | [diff] [blame] | 745 | .set_promisc = tsec_set_promisc, |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 746 | }; |
| 747 | |
Hou Zhiqiang | 5966b6d | 2020-07-16 18:09:14 +0800 | [diff] [blame] | 748 | static struct tsec_data etsec2_data = { |
| 749 | .mdio_regs_off = TSEC_MDIO_REGS_OFFSET, |
| 750 | }; |
| 751 | |
| 752 | static struct tsec_data gianfar_data = { |
| 753 | .mdio_regs_off = 0x0, |
| 754 | }; |
| 755 | |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 756 | static const struct udevice_id tsec_ids[] = { |
Hou Zhiqiang | 5966b6d | 2020-07-16 18:09:14 +0800 | [diff] [blame] | 757 | { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data }, |
| 758 | { .compatible = "gianfar", .data = (ulong)&gianfar_data }, |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 759 | { } |
| 760 | }; |
| 761 | |
| 762 | U_BOOT_DRIVER(eth_tsec) = { |
| 763 | .name = "tsec", |
| 764 | .id = UCLASS_ETH, |
| 765 | .of_match = tsec_ids, |
| 766 | .probe = tsec_probe, |
| 767 | .remove = tsec_remove, |
| 768 | .ops = &tsec_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 769 | .priv_auto = sizeof(struct tsec_private), |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 770 | .plat_auto = sizeof(struct eth_pdata), |
Bin Meng | 1048f61 | 2016-01-11 22:41:24 -0800 | [diff] [blame] | 771 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
| 772 | }; |