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Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +01001/*
2 * Copyright (C) 2004-2007 ARM Limited.
3 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * As a special exception, if other files instantiate templates or use macros
19 * or inline functions from this file, or you compile this file and link it
20 * with other works to produce a work based on this file, this file does not
21 * by itself cause the resulting work to be covered by the GNU General Public
22 * License. However the source code for this file must still be made available
23 * in accordance with section (3) of the GNU General Public License.
24
25 * This exception does not invalidate any other reasons why a work based on
26 * this file might be covered by the GNU General Public License.
27 */
28
29#include <common.h>
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +053030#include <serial.h>
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010031
Alexander Merkle79bb2f62015-03-19 18:37:19 +010032#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010033/*
Alexander Merkle79bb2f62015-03-19 18:37:19 +010034 * ARMV6 & ARMV7
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010035 */
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020036#define DCC_RBIT (1 << 30)
37#define DCC_WBIT (1 << 29)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010038
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020039#define write_dcc(x) \
40 __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010041
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020042#define read_dcc(x) \
43 __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010044
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020045#define status_dcc(x) \
46 __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010047
Jean-Christophe PLAGNIOL-VILLARD195bb7c2009-05-15 23:47:14 +020048#elif defined(CONFIG_CPU_XSCALE)
49/*
50 * XSCALE
51 */
52#define DCC_RBIT (1 << 31)
53#define DCC_WBIT (1 << 28)
54
55#define write_dcc(x) \
56 __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
57
58#define read_dcc(x) \
59 __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
60
61#define status_dcc(x) \
62 __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
63
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020064#else
65#define DCC_RBIT (1 << 0)
66#define DCC_WBIT (1 << 1)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010067
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020068#define write_dcc(x) \
69 __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010070
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020071#define read_dcc(x) \
72 __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010073
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020074#define status_dcc(x) \
75 __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
76
77#endif
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010078
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020079#define can_read_dcc(x) do { \
80 status_dcc(x); \
81 x &= DCC_RBIT; \
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010082 } while (0);
83
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020084#define can_write_dcc(x) do { \
85 status_dcc(x); \
86 x &= DCC_WBIT; \
87 x = (x == 0); \
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010088 } while (0);
89
90#define TIMEOUT_COUNT 0x4000000
91
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +053092static int arm_dcc_init(void)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010093{
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010094 return 0;
95}
96
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +053097static int arm_dcc_getc(void)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010098{
99 int ch;
100 register unsigned int reg;
101
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200102 do {
103 can_read_dcc(reg);
104 } while (!reg);
105 read_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100106
107 return ch;
108}
109
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530110static void arm_dcc_putc(char ch)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100111{
112 register unsigned int reg;
113 unsigned int timeout_count = TIMEOUT_COUNT;
114
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200115 while (--timeout_count) {
116 can_write_dcc(reg);
117 if (reg)
118 break;
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100119 }
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200120 if (timeout_count == 0)
121 return;
122 else
123 write_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100124}
125
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530126static int arm_dcc_tstc(void)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100127{
128 register unsigned int reg;
129
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200130 can_read_dcc(reg);
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100131
132 return reg;
133}
134
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530135static void arm_dcc_setbrg(void)
136{
137}
138
139static struct serial_device arm_dcc_drv = {
140 .name = "arm_dcc",
141 .start = arm_dcc_init,
142 .stop = NULL,
143 .setbrg = arm_dcc_setbrg,
144 .putc = arm_dcc_putc,
Axel Lin1d7b3962013-08-17 15:39:34 +0800145 .puts = default_serial_puts,
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530146 .getc = arm_dcc_getc,
147 .tstc = arm_dcc_tstc,
148};
149
150void arm_dcc_initialize(void)
151{
152 serial_register(&arm_dcc_drv);
153}
154
Michal Simek0828cf22013-01-22 23:40:06 +0000155__weak struct serial_device *default_serial_console(void)
156{
Jagannadha Sutradharudu Teki00de0ed2013-08-04 01:22:25 +0530157 return &arm_dcc_drv;
Michal Simek0828cf22013-01-22 23:40:06 +0000158}