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Kumar Galad5a1fb92008-08-26 21:34:55 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
Tom Rinie2378802016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Kumar Galad5a1fb92008-08-26 21:34:55 -05005 */
6
7#include <common.h>
8#include <asm/io.h>
York Sunf0626592013-09-30 09:22:09 -07009#include <fsl_ddr_sdram.h>
Kumar Galad5a1fb92008-08-26 21:34:55 -050010
11#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
12#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
13#endif
14
15void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
York Sun5e155552013-06-25 11:37:48 -070016 unsigned int ctrl_num, int step)
Kumar Galad5a1fb92008-08-26 21:34:55 -050017{
18 unsigned int i;
York Suna21803d2013-11-18 10:29:32 -080019 struct ccsr_ddr __iomem *ddr =
20 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
Kumar Galad5a1fb92008-08-26 21:34:55 -050021
22 if (ctrl_num != 0) {
23 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
24 return;
25 }
26
27 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
28 if (i == 0) {
29 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
30 out_be32(&ddr->cs0_config, regs->cs[i].config);
31
32 } else if (i == 1) {
33 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
34 out_be32(&ddr->cs1_config, regs->cs[i].config);
35
36 } else if (i == 2) {
37 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
38 out_be32(&ddr->cs2_config, regs->cs[i].config);
39
40 } else if (i == 3) {
41 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
42 out_be32(&ddr->cs3_config, regs->cs[i].config);
43 }
44 }
45
46 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
47 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
48 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
49 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
York Sun32be34d2016-11-16 11:23:23 -080050#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
Kumar Galad5a1fb92008-08-26 21:34:55 -050051 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
52#endif
53
54 /*
55 * 200 painful micro-seconds must elapse between
56 * the DDR clock setup and the DDR config enable.
57 */
58 udelay(200);
59 asm volatile("sync;isync");
60
61 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
62
63 asm("sync;isync;msync");
64 udelay(500);
65}
66
67#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
Kumar Galad5a1fb92008-08-26 21:34:55 -050068/*
69 * Initialize all of memory for ECC, then enable errors.
70 */
71
72void
73ddr_enable_ecc(unsigned int dram_size)
74{
York Suna21803d2013-11-18 10:29:32 -080075 struct ccsr_ddr __iomem *ddr =
76 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
Kumar Galad5a1fb92008-08-26 21:34:55 -050077
Peter Tyser4e928b52009-06-30 17:15:48 -050078 dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
Kumar Galad5a1fb92008-08-26 21:34:55 -050079
80 /*
81 * Enable errors for ECC.
82 */
83 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
84 ddr->err_disable = 0x00000000;
85 asm("sync;isync;msync");
86 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
87}
88
89#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */