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git01.mediatek.com / filogic / uboot / 6be6a2fc36511006a2fa20be432c9b0fac445f06 / . / arch / arm / include / asm / arch-tegra20 / clock-tables.h
blob: 861b3d5d07ce2089d9098465c622a1cd00a18353 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]2/*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]5 */
6
7/* Tegra20 clock PLL tables */
8
9#ifndef _CLOCK_TABLES_H_
10#define _CLOCK_TABLES_H_
11
12/* The PLLs supported by the hardware */
13enum clock_id {
14 CLOCK_ID_FIRST,
15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
16 CLOCK_ID_MEMORY,
17 CLOCK_ID_PERIPH,
18 CLOCK_ID_AUDIO,
19 CLOCK_ID_USB,
20 CLOCK_ID_DISPLAY,
21
22 /* now the simple ones */
23 CLOCK_ID_FIRST_SIMPLE,
24 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
25 CLOCK_ID_EPCI,
26 CLOCK_ID_SFROM32KHZ,
27
28 /* These are the base clocks (inputs to the Tegra SOC) */
29 CLOCK_ID_32KHZ,
30 CLOCK_ID_OSC,
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200[diff] [blame]31 CLOCK_ID_CLK_M,
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]32
33 CLOCK_ID_COUNT, /* number of clocks */
34 CLOCK_ID_NONE = -1,
35};
36
37/* The clocks supported by the hardware */
38enum periph_id {
39 PERIPH_ID_FIRST,
40
41 /* Low word: 31:0 */
42 PERIPH_ID_CPU = PERIPH_ID_FIRST,
43 PERIPH_ID_RESERVED1,
44 PERIPH_ID_RESERVED2,
45 PERIPH_ID_AC97,
46 PERIPH_ID_RTC,
47 PERIPH_ID_TMR,
48 PERIPH_ID_UART1,
49 PERIPH_ID_UART2,
50
51 /* 8 */
52 PERIPH_ID_GPIO,
53 PERIPH_ID_SDMMC2,
54 PERIPH_ID_SPDIF,
55 PERIPH_ID_I2S1,
56 PERIPH_ID_I2C1,
57 PERIPH_ID_NDFLASH,
58 PERIPH_ID_SDMMC1,
59 PERIPH_ID_SDMMC4,
60
61 /* 16 */
62 PERIPH_ID_TWC,
63 PERIPH_ID_PWM,
64 PERIPH_ID_I2S2,
65 PERIPH_ID_EPP,
66 PERIPH_ID_VI,
67 PERIPH_ID_2D,
68 PERIPH_ID_USBD,
69 PERIPH_ID_ISP,
70
71 /* 24 */
72 PERIPH_ID_3D,
73 PERIPH_ID_IDE,
74 PERIPH_ID_DISP2,
75 PERIPH_ID_DISP1,
76 PERIPH_ID_HOST1X,
77 PERIPH_ID_VCP,
78 PERIPH_ID_RESERVED30,
79 PERIPH_ID_CACHE2,
80
81 /* Middle word: 63:32 */
82 PERIPH_ID_MEM,
83 PERIPH_ID_AHBDMA,
84 PERIPH_ID_APBDMA,
85 PERIPH_ID_RESERVED35,
86 PERIPH_ID_KBC,
87 PERIPH_ID_STAT_MON,
88 PERIPH_ID_PMC,
89 PERIPH_ID_FUSE,
90
91 /* 40 */
92 PERIPH_ID_KFUSE,
93 PERIPH_ID_SBC1,
94 PERIPH_ID_SNOR,
95 PERIPH_ID_SPI1,
96 PERIPH_ID_SBC2,
97 PERIPH_ID_XIO,
98 PERIPH_ID_SBC3,
99 PERIPH_ID_DVC_I2C,
100
101 /* 48 */
102 PERIPH_ID_DSI,
103 PERIPH_ID_TVO,
104 PERIPH_ID_MIPI,
105 PERIPH_ID_HDMI,
106 PERIPH_ID_CSI,
107 PERIPH_ID_TVDAC,
108 PERIPH_ID_I2C2,
109 PERIPH_ID_UART3,
110
111 /* 56 */
112 PERIPH_ID_RESERVED56,
113 PERIPH_ID_EMC,
114 PERIPH_ID_USB2,
115 PERIPH_ID_USB3,
116 PERIPH_ID_MPE,
117 PERIPH_ID_VDE,
118 PERIPH_ID_BSEA,
119 PERIPH_ID_BSEV,
120
121 /* Upper word 95:64 */
122 PERIPH_ID_SPEEDO,
123 PERIPH_ID_UART4,
124 PERIPH_ID_UART5,
125 PERIPH_ID_I2C3,
126 PERIPH_ID_SBC4,
127 PERIPH_ID_SDMMC3,
128 PERIPH_ID_PCIE,
129 PERIPH_ID_OWR,
130
131 /* 72 */
132 PERIPH_ID_AFI,
133 PERIPH_ID_CORESIGHT,
Thierry Reding289fc682014-12-09 22:25:07 -0700[diff] [blame]134 PERIPH_ID_PCIEXCLK,
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]135 PERIPH_ID_AVPUCQ,
136 PERIPH_ID_RESERVED76,
137 PERIPH_ID_RESERVED77,
138 PERIPH_ID_RESERVED78,
139 PERIPH_ID_RESERVED79,
140
141 /* 80 */
142 PERIPH_ID_RESERVED80,
143 PERIPH_ID_RESERVED81,
144 PERIPH_ID_RESERVED82,
145 PERIPH_ID_RESERVED83,
146 PERIPH_ID_IRAMA,
147 PERIPH_ID_IRAMB,
148 PERIPH_ID_IRAMC,
149 PERIPH_ID_IRAMD,
150
151 /* 88 */
152 PERIPH_ID_CRAM2,
Lucas Stache6941782012-09-25 09:59:12 +0000[diff] [blame]153 PERIPH_ID_SYNC_CLK_DOUBLER,
154 PERIPH_ID_CLK_M_DOUBLER,
155 PERIPH_ID_RESERVED91,
156 PERIPH_ID_SUS_OUT,
157 PERIPH_ID_DEV2_OUT,
158 PERIPH_ID_DEV1_OUT,
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]159
160 PERIPH_ID_COUNT,
161 PERIPH_ID_NONE = -1,
162};
163
Lucas Stachf7ee2a42012-09-25 20:21:13 +0000[diff] [blame]164enum pll_out_id {
165 PLL_OUT1,
166 PLL_OUT2,
167 PLL_OUT3,
168 PLL_OUT4
169};
170
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]171/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
172#define PERIPH_REG(id) ((id) >> 5)
173
174/* Mask value for a clock (within PERIPH_REG(id)) */
175#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
176
177/* return 1 if a PLL ID is in range, and not a simple PLL */
178#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
179 (id) < CLOCK_ID_FIRST_SIMPLE)
180
Tom Warren795f9d72013-01-23 14:01:01 -0700[diff] [blame]181/* return 1 if a peripheral ID is in range */
182#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
183 (id) < PERIPH_ID_COUNT)
184
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]185#endif /* _CLOCK_TABLES_H_ */