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git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm64 / qcom / sa8295p-adp.dts
blob: fd253942e5e5cdc42f713459a4344081ca049841 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11#include <dt-bindings/spmi/spmi.h>
12
13#include "sa8540p.dtsi"
14#include "sa8540p-pmics.dtsi"
15
16/ {
17 model = "Qualcomm SA8295P ADP";
18 compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
19
20 aliases {
21 serial0 = &uart17;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200n8";
26 };
27
28 dp2-connector {
29 compatible = "dp-connector";
30 label = "DP2";
31 type = "mini";
32
33 hpd-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
34
35 port {
36 dp2_connector_in: endpoint {
37 remote-endpoint = <&mdss1_dp0_phy_out>;
38 };
39 };
40 };
41
42 dp3-connector {
43 compatible = "dp-connector";
44 label = "DP3";
45 type = "mini";
46
47 hpd-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
48
49 port {
50 dp3_connector_in: endpoint {
51 remote-endpoint = <&mdss1_dp1_phy_out>;
52 };
53 };
54 };
55
56 edp0-connector {
57 compatible = "dp-connector";
58 label = "EDP0";
59 type = "mini";
60
61 hpd-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
62
63 port {
64 edp0_connector_in: endpoint {
65 remote-endpoint = <&mdss0_dp2_phy_out>;
66 };
67 };
68 };
69
70 edp1-connector {
71 compatible = "dp-connector";
72 label = "EDP1";
73 type = "mini";
74
75 hpd-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
76
77 port {
78 edp1_connector_in: endpoint {
79 remote-endpoint = <&mdss0_dp3_phy_out>;
80 };
81 };
82 };
83
84 edp2-connector {
85 compatible = "dp-connector";
86 label = "EDP2";
87 type = "mini";
88
89 hpd-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
90
91 port {
92 edp2_connector_in: endpoint {
93 remote-endpoint = <&mdss1_dp2_phy_out>;
94 };
95 };
96 };
97
98 edp3-connector {
99 compatible = "dp-connector";
100 label = "EDP3";
101 type = "mini";
102
103 hpd-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
104
105 port {
106 edp3_connector_in: endpoint {
107 remote-endpoint = <&mdss1_dp3_phy_out>;
108 };
109 };
110 };
111};
112
113&apps_rsc {
114 regulators-0 {
115 compatible = "qcom,pm8150-rpmh-regulators";
116 qcom,pmic-id = "a";
117
118 vreg_l3a: ldo3 {
119 regulator-name = "vreg_l3a";
120 regulator-min-microvolt = <1200000>;
121 regulator-max-microvolt = <1208000>;
122 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
123 };
124
125 vreg_l5a: ldo5 {
126 regulator-name = "vreg_l5a";
127 regulator-min-microvolt = <912000>;
128 regulator-max-microvolt = <912000>;
129 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
130 };
131
132 vreg_l7a: ldo7 {
133 regulator-name = "vreg_l7a";
134 regulator-min-microvolt = <1800000>;
135 regulator-max-microvolt = <1800000>;
136 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
137 };
138
139 vreg_l13a: ldo13 {
140 regulator-name = "vreg_l13a";
141 regulator-min-microvolt = <3072000>;
142 regulator-max-microvolt = <3072000>;
143 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
144 };
145
146 vreg_l11a: ldo11 {
147 regulator-name = "vreg_l11a";
148 regulator-min-microvolt = <880000>;
149 regulator-max-microvolt = <880000>;
150 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
151 };
152 };
153
154 regulators-1 {
155 compatible = "qcom,pm8150-rpmh-regulators";
156 qcom,pmic-id = "c";
157
158 vreg_l1c: ldo1 {
159 regulator-name = "vreg_l1c";
160 regulator-min-microvolt = <912000>;
161 regulator-max-microvolt = <912000>;
162 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
163 };
164
165 vreg_l2c: ldo2 {
166 regulator-name = "vreg_l2c";
167 regulator-min-microvolt = <3072000>;
168 regulator-max-microvolt = <3072000>;
169 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
170 };
171
172 vreg_l3c: ldo3 {
173 regulator-name = "vreg_l3c";
174 regulator-min-microvolt = <1200000>;
175 regulator-max-microvolt = <1200000>;
176 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
177 regulator-allow-set-load;
178 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
179 RPMH_REGULATOR_MODE_HPM>;
180 };
181
182 vreg_l4c: ldo4 {
183 regulator-name = "vreg_l4c";
184 regulator-min-microvolt = <1200000>;
185 regulator-max-microvolt = <1208000>;
186 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
187 };
188
189 vreg_l6c: ldo6 {
190 regulator-name = "vreg_l6c";
191 regulator-min-microvolt = <1200000>;
192 regulator-max-microvolt = <1200000>;
193 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
194 regulator-allow-set-load;
195 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
196 RPMH_REGULATOR_MODE_HPM>;
197 };
198
199 vreg_l7c: ldo7 {
200 regulator-name = "vreg_l7c";
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <1800000>;
203 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
204 };
205
206 vreg_l10c: ldo10 {
207 regulator-name = "vreg_l10c";
208 regulator-min-microvolt = <2504000>;
209 regulator-max-microvolt = <2504000>;
210 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
211 regulator-allow-set-load;
212 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
213 RPMH_REGULATOR_MODE_HPM>;
214 };
215
216 vreg_l17c: ldo17 {
217 regulator-name = "vreg_l17c";
218 regulator-min-microvolt = <2504000>;
219 regulator-max-microvolt = <2504000>;
220 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
221 regulator-allow-set-load;
222 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
223 RPMH_REGULATOR_MODE_HPM>;
224 };
225 };
226
227 regulators-2 {
228 compatible = "qcom,pm8150-rpmh-regulators";
229 qcom,pmic-id = "g";
230
231 vreg_l3g: ldo3 {
232 regulator-name = "vreg_l3g";
233 regulator-min-microvolt = <1200000>;
234 regulator-max-microvolt = <1200000>;
235 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
236 };
237
238 vreg_l7g: ldo7 {
239 regulator-name = "vreg_l7g";
240 regulator-min-microvolt = <1800000>;
241 regulator-max-microvolt = <1800000>;
242 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
243 };
244
245 vreg_l8g: ldo8 {
246 regulator-name = "vreg_l8g";
247 regulator-min-microvolt = <912000>;
248 regulator-max-microvolt = <912000>;
249 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
250 };
251
252 vreg_l11g: ldo11 {
253 regulator-name = "vreg_l11g";
254 regulator-min-microvolt = <912000>;
255 regulator-max-microvolt = <912000>;
256 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
257 };
258 };
259};
260
261&dispcc0 {
262 status = "okay";
263};
264
265&dispcc1 {
266 status = "okay";
267};
268
269&mdss0 {
270 status = "okay";
271};
272
273&mdss0_dp2 {
274 data-lanes = <0 1 2 3>;
275
276 status = "okay";
277
278 ports {
279 port@1 {
280 reg = <1>;
281 mdss0_dp2_phy_out: endpoint {
282 remote-endpoint = <&edp0_connector_in>;
283 };
284 };
285 };
286};
287
288&mdss0_dp2_phy {
289 vdda-phy-supply = <&vreg_l8g>;
290 vdda-pll-supply = <&vreg_l3g>;
291
292 status = "okay";
293};
294
295&mdss0_dp3 {
296 data-lanes = <0 1 2 3>;
297
298 status = "okay";
299
300 ports {
301 port@1 {
302 reg = <1>;
303 mdss0_dp3_phy_out: endpoint {
304 remote-endpoint = <&edp1_connector_in>;
305 };
306 };
307 };
308};
309
310&mdss0_dp3_phy {
311 vdda-phy-supply = <&vreg_l8g>;
312 vdda-pll-supply = <&vreg_l3g>;
313
314 status = "okay";
315};
316
317&mdss1 {
318 status = "okay";
319};
320
321&mdss1_dp0 {
322 data-lanes = <0 1 2 3>;
323
324 status = "okay";
325
326 ports {
327 port@1 {
328 reg = <1>;
329 mdss1_dp0_phy_out: endpoint {
330 remote-endpoint = <&dp2_connector_in>;
331 };
332 };
333 };
334};
335
336&mdss1_dp0_phy {
337 vdda-phy-supply = <&vreg_l11g>;
338 vdda-pll-supply = <&vreg_l3g>;
339
340 status = "okay";
341};
342
343&mdss1_dp1 {
344 data-lanes = <0 1 2 3>;
345
346 status = "okay";
347
348 ports {
349 port@1 {
350 reg = <1>;
351 mdss1_dp1_phy_out: endpoint {
352 remote-endpoint = <&dp3_connector_in>;
353 };
354 };
355 };
356};
357
358&mdss1_dp1_phy {
359 vdda-phy-supply = <&vreg_l11g>;
360 vdda-pll-supply = <&vreg_l3g>;
361
362 status = "okay";
363};
364
365&mdss1_dp2 {
366 data-lanes = <0 1 2 3>;
367
368 status = "okay";
369
370 ports {
371 port@1 {
372 reg = <1>;
373 mdss1_dp2_phy_out: endpoint {
374 remote-endpoint = <&edp2_connector_in>;
375 };
376 };
377 };
378};
379
380&mdss1_dp2_phy {
381 vdda-phy-supply = <&vreg_l11g>;
382 vdda-pll-supply = <&vreg_l3g>;
383
384 status = "okay";
385};
386
387&mdss1_dp3 {
388 data-lanes = <0 1 2 3>;
389
390 status = "okay";
391
392 ports {
393 port@1 {
394 reg = <1>;
395 mdss1_dp3_phy_out: endpoint {
396 remote-endpoint = <&edp3_connector_in>;
397 };
398 };
399 };
400};
401
402&mdss1_dp3_phy {
403 vdda-phy-supply = <&vreg_l11g>;
404 vdda-pll-supply = <&vreg_l3g>;
405
406 status = "okay";
407};
408
409&pcie2a {
410 perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
411 wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
412
413 pinctrl-names = "default";
414 pinctrl-0 = <&pcie2a_default>;
415
416 status = "okay";
417};
418
419&pcie2a_phy {
420 vdda-phy-supply = <&vreg_l11a>;
421 vdda-pll-supply = <&vreg_l3a>;
422
423 status = "okay";
424};
425
426&pcie3a {
427 num-lanes = <2>;
428
429 perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
430 wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
431
432 pinctrl-names = "default";
433 pinctrl-0 = <&pcie3a_default>;
434
435 status = "okay";
436};
437
438&pcie3a_phy {
439 vdda-phy-supply = <&vreg_l11a>;
440 vdda-pll-supply = <&vreg_l3a>;
441
442 status = "okay";
443};
444
445&pcie3b {
446 perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
447 wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
448
449 pinctrl-names = "default";
450 pinctrl-0 = <&pcie3b_default>;
451
452 status = "okay";
453};
454
455&pcie3b_phy {
456 vdda-phy-supply = <&vreg_l11a>;
457 vdda-pll-supply = <&vreg_l3a>;
458
459 status = "okay";
460};
461
462&pcie4 {
463 perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
464 wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
465
466 pinctrl-names = "default";
467 pinctrl-0 = <&pcie4_default>;
468
469 status = "okay";
470};
471
472&pcie4_phy {
473 vdda-phy-supply = <&vreg_l11a>;
474 vdda-pll-supply = <&vreg_l3a>;
475
476 status = "okay";
477};
478
479&qup2 {
480 status = "okay";
481};
482
483&remoteproc_adsp {
484 firmware-name = "qcom/sa8540p/adsp.mbn";
485 status = "okay";
486};
487
488&remoteproc_nsp0 {
489 firmware-name = "qcom/sa8540p/cdsp.mbn";
490 status = "okay";
491};
492
493&remoteproc_nsp1 {
494 firmware-name = "qcom/sa8540p/cdsp1.mbn";
495 status = "okay";
496};
497
498&uart17 {
499 compatible = "qcom,geni-debug-uart";
500 status = "okay";
501};
502
503&ufs_mem_hc {
504 reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
505
506 vcc-supply = <&vreg_l17c>;
507 vcc-max-microamp = <800000>;
508 vccq-supply = <&vreg_l6c>;
509 vccq-max-microamp = <900000>;
510
511 status = "okay";
512};
513
514&ufs_mem_phy {
515 vdda-phy-supply = <&vreg_l8g>;
516 vdda-pll-supply = <&vreg_l3g>;
517
518 status = "okay";
519};
520
521&ufs_card_hc {
522 reset-gpios = <&tlmm 229 GPIO_ACTIVE_LOW>;
523
524 vcc-supply = <&vreg_l10c>;
525 vcc-max-microamp = <800000>;
526 vccq-supply = <&vreg_l3c>;
527 vccq-max-microamp = <900000>;
528
529 status = "okay";
530};
531
532&ufs_card_phy {
533 vdda-phy-supply = <&vreg_l8g>;
534 vdda-pll-supply = <&vreg_l3g>;
535
536 status = "okay";
537};
538
539&usb_0 {
540 status = "okay";
541};
542
543&usb_0_dwc3 {
544 /* TODO: Define USB-C connector properly */
545 dr_mode = "peripheral";
546};
547
548&usb_0_hsphy {
549 vdda-pll-supply = <&vreg_l5a>;
550 vdda18-supply = <&vreg_l7a>;
551 vdda33-supply = <&vreg_l13a>;
552
553 status = "okay";
554};
555
556&usb_0_qmpphy {
557 vdda-phy-supply = <&vreg_l3a>;
558 vdda-pll-supply = <&vreg_l5a>;
559
560 status = "okay";
561};
562
563&usb_1 {
564 status = "okay";
565};
566
567&usb_1_dwc3 {
568 /* TODO: Define USB-C connector properly */
569 dr_mode = "host";
570};
571
572&usb_1_hsphy {
573 vdda-pll-supply = <&vreg_l1c>;
574 vdda18-supply = <&vreg_l7c>;
575 vdda33-supply = <&vreg_l2c>;
576
577 status = "okay";
578};
579
580&usb_1_qmpphy {
581 vdda-phy-supply = <&vreg_l4c>;
582 vdda-pll-supply = <&vreg_l1c>;
583
584 status = "okay";
585};
586
587&usb_2_hsphy0 {
588 vdda-pll-supply = <&vreg_l5a>;
589 vdda18-supply = <&vreg_l7g>;
590 vdda33-supply = <&vreg_l13a>;
591
592 status = "okay";
593};
594
595&usb_2_hsphy1 {
596 vdda-pll-supply = <&vreg_l5a>;
597 vdda18-supply = <&vreg_l7g>;
598 vdda33-supply = <&vreg_l13a>;
599
600 status = "okay";
601};
602
603&usb_2_hsphy2 {
604 vdda-pll-supply = <&vreg_l5a>;
605 vdda18-supply = <&vreg_l7g>;
606 vdda33-supply = <&vreg_l13a>;
607
608 status = "okay";
609};
610
611&usb_2_hsphy3 {
612 vdda-pll-supply = <&vreg_l5a>;
613 vdda18-supply = <&vreg_l7g>;
614 vdda33-supply = <&vreg_l13a>;
615
616 status = "okay";
617};
618
619&usb_2_qmpphy0 {
620 vdda-phy-supply = <&vreg_l3a>;
621 vdda-pll-supply = <&vreg_l5a>;
622
623 status = "okay";
624};
625
626&usb_2_qmpphy1 {
627 vdda-phy-supply = <&vreg_l3a>;
628 vdda-pll-supply = <&vreg_l5a>;
629
630 status = "okay";
631};
632
633&xo_board_clk {
634 clock-frequency = <38400000>;
635};
636
637/* PINCTRL */
638
639&tlmm {
640 pcie2a_default: pcie2a-default-state {
641 clkreq-n-pins {
642 pins = "gpio142";
643 function = "pcie2a_clkreq";
644 drive-strength = <2>;
645 bias-pull-up;
646 };
647
648 perst-n-pins {
649 pins = "gpio143";
650 function = "gpio";
651 drive-strength = <2>;
652 bias-pull-down;
653 };
654
655 wake-n-pins {
656 pins = "gpio145";
657 function = "gpio";
658 drive-strength = <2>;
659 bias-pull-up;
660 };
661 };
662
663 pcie3a_default: pcie3a-default-state {
664 clkreq-n-pins {
665 pins = "gpio150";
666 function = "pcie3a_clkreq";
667 drive-strength = <2>;
668 bias-pull-up;
669 };
670
671 perst-n-pins {
672 pins = "gpio151";
673 function = "gpio";
674 drive-strength = <2>;
675 bias-pull-down;
676 };
677
678 wake-n-pins {
679 pins = "gpio56";
680 function = "gpio";
681 drive-strength = <2>;
682 bias-pull-up;
683 };
684 };
685
686 pcie3b_default: pcie3b-default-state {
687 clkreq-n-pins {
688 pins = "gpio152";
689 function = "pcie3b_clkreq";
690 drive-strength = <2>;
691 bias-pull-up;
692 };
693
694 perst-n-pins {
695 pins = "gpio153";
696 function = "gpio";
697 drive-strength = <2>;
698 bias-pull-down;
699 };
700
701 wake-n-pins {
702 pins = "gpio130";
703 function = "gpio";
704 drive-strength = <2>;
705 bias-pull-up;
706 };
707 };
708
709 pcie4_default: pcie4-default-state {
710 clkreq-n-pins {
711 pins = "gpio140";
712 function = "pcie4_clkreq";
713 drive-strength = <2>;
714 bias-pull-up;
715 };
716
717 perst-n-pins {
718 pins = "gpio141";
719 function = "gpio";
720 drive-strength = <2>;
721 bias-pull-down;
722 };
723
724 wake-n-pins {
725 pins = "gpio139";
726 function = "gpio";
727 drive-strength = <2>;
728 bias-pull-up;
729 };
730 };
731};