Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * IPQ6018 SoC device tree source |
| 4 | * |
| 5 | * Copyright (c) 2019, The Linux Foundation. All rights reserved. |
| 6 | */ |
| 7 | |
| 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 9 | #include <dt-bindings/clock/qcom,gcc-ipq6018.h> |
| 10 | #include <dt-bindings/reset/qcom,gcc-ipq6018.h> |
| 11 | #include <dt-bindings/clock/qcom,apss-ipq.h> |
| 12 | |
| 13 | / { |
| 14 | #address-cells = <2>; |
| 15 | #size-cells = <2>; |
| 16 | interrupt-parent = <&intc>; |
| 17 | |
| 18 | clocks { |
| 19 | sleep_clk: sleep-clk { |
| 20 | compatible = "fixed-clock"; |
| 21 | clock-frequency = <32000>; |
| 22 | #clock-cells = <0>; |
| 23 | }; |
| 24 | |
| 25 | xo: xo { |
| 26 | compatible = "fixed-clock"; |
| 27 | clock-frequency = <24000000>; |
| 28 | #clock-cells = <0>; |
| 29 | }; |
| 30 | }; |
| 31 | |
| 32 | cpus: cpus { |
| 33 | #address-cells = <1>; |
| 34 | #size-cells = <0>; |
| 35 | |
| 36 | CPU0: cpu@0 { |
| 37 | device_type = "cpu"; |
| 38 | compatible = "arm,cortex-a53"; |
| 39 | reg = <0x0>; |
| 40 | enable-method = "psci"; |
| 41 | next-level-cache = <&L2_0>; |
| 42 | clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| 43 | clock-names = "cpu"; |
| 44 | operating-points-v2 = <&cpu_opp_table>; |
| 45 | cpu-supply = <&ipq6018_s2>; |
| 46 | }; |
| 47 | |
| 48 | CPU1: cpu@1 { |
| 49 | device_type = "cpu"; |
| 50 | compatible = "arm,cortex-a53"; |
| 51 | enable-method = "psci"; |
| 52 | reg = <0x1>; |
| 53 | next-level-cache = <&L2_0>; |
| 54 | clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| 55 | clock-names = "cpu"; |
| 56 | operating-points-v2 = <&cpu_opp_table>; |
| 57 | cpu-supply = <&ipq6018_s2>; |
| 58 | }; |
| 59 | |
| 60 | CPU2: cpu@2 { |
| 61 | device_type = "cpu"; |
| 62 | compatible = "arm,cortex-a53"; |
| 63 | enable-method = "psci"; |
| 64 | reg = <0x2>; |
| 65 | next-level-cache = <&L2_0>; |
| 66 | clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| 67 | clock-names = "cpu"; |
| 68 | operating-points-v2 = <&cpu_opp_table>; |
| 69 | cpu-supply = <&ipq6018_s2>; |
| 70 | }; |
| 71 | |
| 72 | CPU3: cpu@3 { |
| 73 | device_type = "cpu"; |
| 74 | compatible = "arm,cortex-a53"; |
| 75 | enable-method = "psci"; |
| 76 | reg = <0x3>; |
| 77 | next-level-cache = <&L2_0>; |
| 78 | clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| 79 | clock-names = "cpu"; |
| 80 | operating-points-v2 = <&cpu_opp_table>; |
| 81 | cpu-supply = <&ipq6018_s2>; |
| 82 | }; |
| 83 | |
| 84 | L2_0: l2-cache { |
| 85 | compatible = "cache"; |
| 86 | cache-level = <2>; |
| 87 | cache-unified; |
| 88 | }; |
| 89 | }; |
| 90 | |
| 91 | firmware { |
| 92 | scm { |
| 93 | compatible = "qcom,scm-ipq6018", "qcom,scm"; |
| 94 | qcom,dload-mode = <&tcsr 0x6100>; |
| 95 | }; |
| 96 | }; |
| 97 | |
| 98 | cpu_opp_table: opp-table-cpu { |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 99 | compatible = "operating-points-v2-kryo-cpu"; |
| 100 | nvmem-cells = <&cpu_speed_bin>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 101 | opp-shared; |
| 102 | |
| 103 | opp-864000000 { |
| 104 | opp-hz = /bits/ 64 <864000000>; |
| 105 | opp-microvolt = <725000>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 106 | opp-supported-hw = <0xf>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 107 | clock-latency-ns = <200000>; |
| 108 | }; |
| 109 | |
| 110 | opp-1056000000 { |
| 111 | opp-hz = /bits/ 64 <1056000000>; |
| 112 | opp-microvolt = <787500>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 113 | opp-supported-hw = <0xf>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 114 | clock-latency-ns = <200000>; |
| 115 | }; |
| 116 | |
| 117 | opp-1320000000 { |
| 118 | opp-hz = /bits/ 64 <1320000000>; |
| 119 | opp-microvolt = <862500>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 120 | opp-supported-hw = <0x3>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 121 | clock-latency-ns = <200000>; |
| 122 | }; |
| 123 | |
| 124 | opp-1440000000 { |
| 125 | opp-hz = /bits/ 64 <1440000000>; |
| 126 | opp-microvolt = <925000>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 127 | opp-supported-hw = <0x3>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 128 | clock-latency-ns = <200000>; |
| 129 | }; |
| 130 | |
| 131 | opp-1608000000 { |
| 132 | opp-hz = /bits/ 64 <1608000000>; |
| 133 | opp-microvolt = <987500>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 134 | opp-supported-hw = <0x1>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 135 | clock-latency-ns = <200000>; |
| 136 | }; |
| 137 | |
| 138 | opp-1800000000 { |
| 139 | opp-hz = /bits/ 64 <1800000000>; |
| 140 | opp-microvolt = <1062500>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 141 | opp-supported-hw = <0x1>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 142 | clock-latency-ns = <200000>; |
| 143 | }; |
| 144 | }; |
| 145 | |
| 146 | pmuv8: pmu { |
| 147 | compatible = "arm,cortex-a53-pmu"; |
| 148 | interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 149 | }; |
| 150 | |
| 151 | psci: psci { |
| 152 | compatible = "arm,psci-1.0"; |
| 153 | method = "smc"; |
| 154 | }; |
| 155 | |
| 156 | rpm: remoteproc { |
| 157 | compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc"; |
| 158 | |
| 159 | glink-edge { |
| 160 | compatible = "qcom,glink-rpm"; |
| 161 | interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; |
| 162 | qcom,rpm-msg-ram = <&rpm_msg_ram>; |
| 163 | mboxes = <&apcs_glb 0>; |
| 164 | |
| 165 | rpm_requests: rpm-requests { |
| 166 | compatible = "qcom,rpm-ipq6018"; |
| 167 | qcom,glink-channels = "rpm_requests"; |
| 168 | |
| 169 | regulators { |
| 170 | compatible = "qcom,rpm-mp5496-regulators"; |
| 171 | |
| 172 | ipq6018_s2: s2 { |
| 173 | regulator-min-microvolt = <725000>; |
| 174 | regulator-max-microvolt = <1062500>; |
| 175 | regulator-always-on; |
| 176 | }; |
| 177 | }; |
| 178 | }; |
| 179 | }; |
| 180 | }; |
| 181 | |
| 182 | reserved-memory { |
| 183 | #address-cells = <2>; |
| 184 | #size-cells = <2>; |
| 185 | ranges; |
| 186 | |
| 187 | rpm_msg_ram: memory@60000 { |
| 188 | reg = <0x0 0x00060000 0x0 0x6000>; |
| 189 | no-map; |
| 190 | }; |
| 191 | |
| 192 | bootloader@4a100000 { |
| 193 | reg = <0x0 0x4a100000 0x0 0x400000>; |
| 194 | no-map; |
| 195 | }; |
| 196 | |
| 197 | sbl@4a500000 { |
| 198 | reg = <0x0 0x4a500000 0x0 0x100000>; |
| 199 | no-map; |
| 200 | }; |
| 201 | |
| 202 | tz: memory@4a600000 { |
| 203 | reg = <0x0 0x4a600000 0x0 0x400000>; |
| 204 | no-map; |
| 205 | }; |
| 206 | |
| 207 | smem_region: memory@4aa00000 { |
| 208 | reg = <0x0 0x4aa00000 0x0 0x100000>; |
| 209 | no-map; |
| 210 | }; |
| 211 | |
| 212 | q6_region: memory@4ab00000 { |
| 213 | reg = <0x0 0x4ab00000 0x0 0x5500000>; |
| 214 | no-map; |
| 215 | }; |
| 216 | }; |
| 217 | |
| 218 | smem { |
| 219 | compatible = "qcom,smem"; |
| 220 | memory-region = <&smem_region>; |
| 221 | hwlocks = <&tcsr_mutex 3>; |
| 222 | }; |
| 223 | |
| 224 | soc: soc@0 { |
| 225 | #address-cells = <2>; |
| 226 | #size-cells = <2>; |
| 227 | ranges = <0 0 0 0 0x0 0xffffffff>; |
| 228 | dma-ranges; |
| 229 | compatible = "simple-bus"; |
| 230 | |
| 231 | qusb_phy_1: qusb@59000 { |
| 232 | compatible = "qcom,ipq6018-qusb2-phy"; |
| 233 | reg = <0x0 0x00059000 0x0 0x180>; |
| 234 | #phy-cells = <0>; |
| 235 | |
| 236 | clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, |
| 237 | <&xo>; |
| 238 | clock-names = "cfg_ahb", "ref"; |
| 239 | |
| 240 | resets = <&gcc GCC_QUSB2_1_PHY_BCR>; |
| 241 | status = "disabled"; |
| 242 | }; |
| 243 | |
| 244 | ssphy_0: ssphy@78000 { |
| 245 | compatible = "qcom,ipq6018-qmp-usb3-phy"; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 246 | reg = <0x0 0x00078000 0x0 0x1000>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 247 | |
| 248 | clocks = <&gcc GCC_USB0_AUX_CLK>, |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 249 | <&xo>, |
| 250 | <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, |
| 251 | <&gcc GCC_USB0_PIPE_CLK>; |
| 252 | clock-names = "aux", |
| 253 | "ref", |
| 254 | "cfg_ahb", |
| 255 | "pipe"; |
| 256 | clock-output-names = "gcc_usb0_pipe_clk_src"; |
| 257 | #clock-cells = <0>; |
| 258 | #phy-cells = <0>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 259 | |
| 260 | resets = <&gcc GCC_USB0_PHY_BCR>, |
| 261 | <&gcc GCC_USB3PHY_0_PHY_BCR>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 262 | reset-names = "phy", |
| 263 | "phy_phy"; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 264 | |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 265 | status = "disabled"; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | qusb_phy_0: qusb@79000 { |
| 269 | compatible = "qcom,ipq6018-qusb2-phy"; |
| 270 | reg = <0x0 0x00079000 0x0 0x180>; |
| 271 | #phy-cells = <0>; |
| 272 | |
| 273 | clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, |
| 274 | <&xo>; |
| 275 | clock-names = "cfg_ahb", "ref"; |
| 276 | |
| 277 | resets = <&gcc GCC_QUSB2_0_PHY_BCR>; |
| 278 | status = "disabled"; |
| 279 | }; |
| 280 | |
| 281 | pcie_phy: phy@84000 { |
| 282 | compatible = "qcom,ipq6018-qmp-pcie-phy"; |
| 283 | reg = <0x0 0x00084000 0x0 0x1000>; |
| 284 | status = "disabled"; |
| 285 | |
| 286 | clocks = <&gcc GCC_PCIE0_AUX_CLK>, |
| 287 | <&gcc GCC_PCIE0_AHB_CLK>, |
| 288 | <&gcc GCC_PCIE0_PIPE_CLK>; |
| 289 | clock-names = "aux", |
| 290 | "cfg_ahb", |
| 291 | "pipe"; |
| 292 | |
| 293 | clock-output-names = "gcc_pcie0_pipe_clk_src"; |
| 294 | #clock-cells = <0>; |
| 295 | |
| 296 | #phy-cells = <0>; |
| 297 | |
| 298 | resets = <&gcc GCC_PCIE0_PHY_BCR>, |
| 299 | <&gcc GCC_PCIE0PHY_PHY_BCR>; |
| 300 | reset-names = "phy", |
| 301 | "common"; |
| 302 | }; |
| 303 | |
| 304 | mdio: mdio@90000 { |
| 305 | #address-cells = <1>; |
| 306 | #size-cells = <0>; |
| 307 | compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; |
| 308 | reg = <0x0 0x00090000 0x0 0x64>; |
| 309 | clocks = <&gcc GCC_MDIO_AHB_CLK>; |
| 310 | clock-names = "gcc_mdio_ahb_clk"; |
| 311 | status = "disabled"; |
| 312 | }; |
| 313 | |
| 314 | qfprom: efuse@a4000 { |
| 315 | compatible = "qcom,ipq6018-qfprom", "qcom,qfprom"; |
| 316 | reg = <0x0 0x000a4000 0x0 0x2000>; |
| 317 | #address-cells = <1>; |
| 318 | #size-cells = <1>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 319 | |
| 320 | cpu_speed_bin: cpu-speed-bin@135 { |
| 321 | reg = <0x135 0x1>; |
| 322 | bits = <7 1>; |
| 323 | }; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 324 | }; |
| 325 | |
| 326 | prng: qrng@e3000 { |
| 327 | compatible = "qcom,prng-ee"; |
| 328 | reg = <0x0 0x000e3000 0x0 0x1000>; |
| 329 | clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| 330 | clock-names = "core"; |
| 331 | }; |
| 332 | |
| 333 | cryptobam: dma-controller@704000 { |
| 334 | compatible = "qcom,bam-v1.7.0"; |
| 335 | reg = <0x0 0x00704000 0x0 0x20000>; |
| 336 | interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; |
| 337 | clocks = <&gcc GCC_CRYPTO_AHB_CLK>; |
| 338 | clock-names = "bam_clk"; |
| 339 | #dma-cells = <1>; |
| 340 | qcom,ee = <1>; |
| 341 | qcom,controlled-remotely; |
| 342 | }; |
| 343 | |
| 344 | crypto: crypto@73a000 { |
| 345 | compatible = "qcom,crypto-v5.1"; |
| 346 | reg = <0x0 0x0073a000 0x0 0x6000>; |
| 347 | clocks = <&gcc GCC_CRYPTO_AHB_CLK>, |
| 348 | <&gcc GCC_CRYPTO_AXI_CLK>, |
| 349 | <&gcc GCC_CRYPTO_CLK>; |
| 350 | clock-names = "iface", "bus", "core"; |
| 351 | dmas = <&cryptobam 2>, <&cryptobam 3>; |
| 352 | dma-names = "rx", "tx"; |
| 353 | }; |
| 354 | |
| 355 | tlmm: pinctrl@1000000 { |
| 356 | compatible = "qcom,ipq6018-pinctrl"; |
| 357 | reg = <0x0 0x01000000 0x0 0x300000>; |
| 358 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| 359 | gpio-controller; |
| 360 | #gpio-cells = <2>; |
| 361 | gpio-ranges = <&tlmm 0 0 80>; |
| 362 | interrupt-controller; |
| 363 | #interrupt-cells = <2>; |
| 364 | |
| 365 | serial_3_pins: serial3-state { |
| 366 | pins = "gpio44", "gpio45"; |
| 367 | function = "blsp2_uart"; |
| 368 | drive-strength = <8>; |
| 369 | bias-pull-down; |
| 370 | }; |
| 371 | |
| 372 | qpic_pins: qpic-state { |
| 373 | pins = "gpio1", "gpio3", "gpio4", |
| 374 | "gpio5", "gpio6", "gpio7", |
| 375 | "gpio8", "gpio10", "gpio11", |
| 376 | "gpio12", "gpio13", "gpio14", |
| 377 | "gpio15", "gpio17"; |
| 378 | function = "qpic_pad"; |
| 379 | drive-strength = <8>; |
| 380 | bias-disable; |
| 381 | }; |
| 382 | }; |
| 383 | |
| 384 | gcc: gcc@1800000 { |
| 385 | compatible = "qcom,gcc-ipq6018"; |
| 386 | reg = <0x0 0x01800000 0x0 0x80000>; |
| 387 | clocks = <&xo>, <&sleep_clk>; |
| 388 | clock-names = "xo", "sleep_clk"; |
| 389 | #clock-cells = <1>; |
| 390 | #reset-cells = <1>; |
| 391 | }; |
| 392 | |
| 393 | tcsr_mutex: hwlock@1905000 { |
| 394 | compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; |
| 395 | reg = <0x0 0x01905000 0x0 0x20000>; |
| 396 | #hwlock-cells = <1>; |
| 397 | }; |
| 398 | |
| 399 | tcsr: syscon@1937000 { |
| 400 | compatible = "qcom,tcsr-ipq6018", "syscon"; |
| 401 | reg = <0x0 0x01937000 0x0 0x21000>; |
| 402 | }; |
| 403 | |
| 404 | usb2: usb@70f8800 { |
| 405 | compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; |
| 406 | reg = <0x0 0x070f8800 0x0 0x400>; |
| 407 | #address-cells = <2>; |
| 408 | #size-cells = <2>; |
| 409 | ranges; |
| 410 | clocks = <&gcc GCC_USB1_MASTER_CLK>, |
| 411 | <&gcc GCC_USB1_SLEEP_CLK>, |
| 412 | <&gcc GCC_USB1_MOCK_UTMI_CLK>; |
| 413 | clock-names = "core", |
| 414 | "sleep", |
| 415 | "mock_utmi"; |
| 416 | |
| 417 | assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, |
| 418 | <&gcc GCC_USB1_MOCK_UTMI_CLK>; |
| 419 | assigned-clock-rates = <133330000>, |
| 420 | <24000000>; |
| 421 | resets = <&gcc GCC_USB1_BCR>; |
| 422 | status = "disabled"; |
| 423 | |
| 424 | dwc_1: usb@7000000 { |
| 425 | compatible = "snps,dwc3"; |
| 426 | reg = <0x0 0x07000000 0x0 0xcd00>; |
| 427 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| 428 | phys = <&qusb_phy_1>; |
| 429 | phy-names = "usb2-phy"; |
| 430 | tx-fifo-resize; |
| 431 | snps,is-utmi-l1-suspend; |
| 432 | snps,hird-threshold = /bits/ 8 <0x0>; |
| 433 | snps,dis_u2_susphy_quirk; |
| 434 | snps,dis_u3_susphy_quirk; |
| 435 | dr_mode = "host"; |
| 436 | }; |
| 437 | }; |
| 438 | |
| 439 | blsp_dma: dma-controller@7884000 { |
| 440 | compatible = "qcom,bam-v1.7.0"; |
| 441 | reg = <0x0 0x07884000 0x0 0x2b000>; |
| 442 | interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; |
| 443 | clocks = <&gcc GCC_BLSP1_AHB_CLK>; |
| 444 | clock-names = "bam_clk"; |
| 445 | #dma-cells = <1>; |
| 446 | qcom,ee = <0>; |
| 447 | }; |
| 448 | |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 449 | blsp1_uart1: serial@78af000 { |
| 450 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 451 | reg = <0x0 0x78af000 0x0 0x200>; |
| 452 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 453 | clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, |
| 454 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 455 | clock-names = "core", "iface"; |
| 456 | status = "disabled"; |
| 457 | }; |
| 458 | |
| 459 | blsp1_uart2: serial@78b0000 { |
| 460 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 461 | reg = <0x0 0x78b0000 0x0 0x200>; |
| 462 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 463 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, |
| 464 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 465 | clock-names = "core", "iface"; |
| 466 | status = "disabled"; |
| 467 | }; |
| 468 | |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 469 | blsp1_uart3: serial@78b1000 { |
| 470 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 471 | reg = <0x0 0x078b1000 0x0 0x200>; |
| 472 | interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; |
| 473 | clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, |
| 474 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 475 | clock-names = "core", "iface"; |
| 476 | status = "disabled"; |
| 477 | }; |
| 478 | |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 479 | blsp1_uart4: serial@78b2000 { |
| 480 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 481 | reg = <0x0 0x078b2000 0x0 0x200>; |
| 482 | interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; |
| 483 | clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, |
| 484 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 485 | clock-names = "core", "iface"; |
| 486 | status = "disabled"; |
| 487 | }; |
| 488 | |
| 489 | blsp1_uart5: serial@78b3000 { |
| 490 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 491 | reg = <0x0 0x78b3000 0x0 0x200>; |
| 492 | interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; |
| 493 | clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, |
| 494 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 495 | clock-names = "core", "iface"; |
| 496 | status = "disabled"; |
| 497 | }; |
| 498 | |
| 499 | blsp1_uart6: serial@78b4000 { |
| 500 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 501 | reg = <0x0 0x078b4000 0x0 0x200>; |
| 502 | interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; |
| 503 | clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, |
| 504 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 505 | clock-names = "core", "iface"; |
| 506 | status = "disabled"; |
| 507 | }; |
| 508 | |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 509 | blsp1_spi1: spi@78b5000 { |
| 510 | compatible = "qcom,spi-qup-v2.2.1"; |
| 511 | #address-cells = <1>; |
| 512 | #size-cells = <0>; |
| 513 | reg = <0x0 0x078b5000 0x0 0x600>; |
| 514 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| 515 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, |
| 516 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 517 | clock-names = "core", "iface"; |
| 518 | dmas = <&blsp_dma 12>, <&blsp_dma 13>; |
| 519 | dma-names = "tx", "rx"; |
| 520 | status = "disabled"; |
| 521 | }; |
| 522 | |
| 523 | blsp1_spi2: spi@78b6000 { |
| 524 | compatible = "qcom,spi-qup-v2.2.1"; |
| 525 | #address-cells = <1>; |
| 526 | #size-cells = <0>; |
| 527 | reg = <0x0 0x078b6000 0x0 0x600>; |
| 528 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 529 | clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, |
| 530 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 531 | clock-names = "core", "iface"; |
| 532 | dmas = <&blsp_dma 14>, <&blsp_dma 15>; |
| 533 | dma-names = "tx", "rx"; |
| 534 | status = "disabled"; |
| 535 | }; |
| 536 | |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 537 | blsp1_spi5: spi@78b9000 { |
| 538 | compatible = "qcom,spi-qup-v2.2.1"; |
| 539 | #address-cells = <1>; |
| 540 | #size-cells = <0>; |
| 541 | reg = <0x0 0x078b9000 0x0 0x600>; |
| 542 | interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; |
| 543 | clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, |
| 544 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 545 | clock-names = "core", "iface"; |
| 546 | dmas = <&blsp_dma 20>, <&blsp_dma 21>; |
| 547 | dma-names = "tx", "rx"; |
| 548 | status = "disabled"; |
| 549 | }; |
| 550 | |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 551 | blsp1_i2c2: i2c@78b6000 { |
| 552 | compatible = "qcom,i2c-qup-v2.2.1"; |
| 553 | #address-cells = <1>; |
| 554 | #size-cells = <0>; |
| 555 | reg = <0x0 0x078b6000 0x0 0x600>; |
| 556 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 557 | clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, |
| 558 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 559 | clock-names = "core", "iface"; |
| 560 | clock-frequency = <400000>; |
| 561 | dmas = <&blsp_dma 14>, <&blsp_dma 15>; |
| 562 | dma-names = "tx", "rx"; |
| 563 | status = "disabled"; |
| 564 | }; |
| 565 | |
| 566 | blsp1_i2c3: i2c@78b7000 { |
| 567 | compatible = "qcom,i2c-qup-v2.2.1"; |
| 568 | #address-cells = <1>; |
| 569 | #size-cells = <0>; |
| 570 | reg = <0x0 0x078b7000 0x0 0x600>; |
| 571 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 572 | clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, |
| 573 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 574 | clock-names = "core", "iface"; |
| 575 | clock-frequency = <400000>; |
| 576 | dmas = <&blsp_dma 16>, <&blsp_dma 17>; |
| 577 | dma-names = "tx", "rx"; |
| 578 | status = "disabled"; |
| 579 | }; |
| 580 | |
| 581 | qpic_bam: dma-controller@7984000 { |
| 582 | compatible = "qcom,bam-v1.7.0"; |
| 583 | reg = <0x0 0x07984000 0x0 0x1a000>; |
| 584 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
| 585 | clocks = <&gcc GCC_QPIC_AHB_CLK>; |
| 586 | clock-names = "bam_clk"; |
| 587 | #dma-cells = <1>; |
| 588 | qcom,ee = <0>; |
| 589 | status = "disabled"; |
| 590 | }; |
| 591 | |
| 592 | qpic_nand: nand-controller@79b0000 { |
| 593 | compatible = "qcom,ipq6018-nand"; |
| 594 | reg = <0x0 0x079b0000 0x0 0x10000>; |
| 595 | #address-cells = <1>; |
| 596 | #size-cells = <0>; |
| 597 | clocks = <&gcc GCC_QPIC_CLK>, |
| 598 | <&gcc GCC_QPIC_AHB_CLK>; |
| 599 | clock-names = "core", "aon"; |
| 600 | |
| 601 | dmas = <&qpic_bam 0>, |
| 602 | <&qpic_bam 1>, |
| 603 | <&qpic_bam 2>; |
| 604 | dma-names = "tx", "rx", "cmd"; |
| 605 | pinctrl-0 = <&qpic_pins>; |
| 606 | pinctrl-names = "default"; |
| 607 | status = "disabled"; |
| 608 | }; |
| 609 | |
| 610 | usb3: usb@8af8800 { |
| 611 | compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; |
| 612 | reg = <0x0 0x08af8800 0x0 0x400>; |
| 613 | #address-cells = <2>; |
| 614 | #size-cells = <2>; |
| 615 | ranges; |
| 616 | |
| 617 | clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, |
| 618 | <&gcc GCC_USB0_MASTER_CLK>, |
| 619 | <&gcc GCC_USB0_SLEEP_CLK>, |
| 620 | <&gcc GCC_USB0_MOCK_UTMI_CLK>; |
| 621 | clock-names = "cfg_noc", |
| 622 | "core", |
| 623 | "sleep", |
| 624 | "mock_utmi"; |
| 625 | |
| 626 | assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, |
| 627 | <&gcc GCC_USB0_MASTER_CLK>, |
| 628 | <&gcc GCC_USB0_MOCK_UTMI_CLK>; |
| 629 | assigned-clock-rates = <133330000>, |
| 630 | <133330000>, |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 631 | <24000000>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 632 | |
| 633 | resets = <&gcc GCC_USB0_BCR>; |
| 634 | status = "disabled"; |
| 635 | |
| 636 | dwc_0: usb@8a00000 { |
| 637 | compatible = "snps,dwc3"; |
| 638 | reg = <0x0 0x08a00000 0x0 0xcd00>; |
| 639 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 640 | phys = <&qusb_phy_0>, <&ssphy_0>; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 641 | phy-names = "usb2-phy", "usb3-phy"; |
| 642 | clocks = <&xo>; |
| 643 | clock-names = "ref"; |
| 644 | tx-fifo-resize; |
| 645 | snps,is-utmi-l1-suspend; |
| 646 | snps,hird-threshold = /bits/ 8 <0x0>; |
| 647 | snps,dis_u2_susphy_quirk; |
| 648 | snps,dis_u3_susphy_quirk; |
| 649 | dr_mode = "host"; |
| 650 | }; |
| 651 | }; |
| 652 | |
| 653 | intc: interrupt-controller@b000000 { |
| 654 | compatible = "qcom,msm-qgic2"; |
| 655 | #address-cells = <2>; |
| 656 | #size-cells = <2>; |
| 657 | interrupt-controller; |
| 658 | #interrupt-cells = <3>; |
| 659 | reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ |
| 660 | <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ |
| 661 | <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ |
| 662 | <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ |
| 663 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 664 | ranges = <0 0 0 0xb00a000 0 0xffd>; |
| 665 | |
| 666 | v2m@0 { |
| 667 | compatible = "arm,gic-v2m-frame"; |
| 668 | msi-controller; |
| 669 | reg = <0x0 0x0 0x0 0xffd>; |
| 670 | }; |
| 671 | }; |
| 672 | |
| 673 | watchdog@b017000 { |
| 674 | compatible = "qcom,kpss-wdt"; |
| 675 | interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; |
| 676 | reg = <0x0 0x0b017000 0x0 0x40>; |
| 677 | clocks = <&sleep_clk>; |
| 678 | timeout-sec = <10>; |
| 679 | }; |
| 680 | |
| 681 | apcs_glb: mailbox@b111000 { |
| 682 | compatible = "qcom,ipq6018-apcs-apps-global"; |
| 683 | reg = <0x0 0x0b111000 0x0 0x1000>; |
| 684 | #clock-cells = <1>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 685 | clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; |
| 686 | clock-names = "pll", "xo", "gpll0"; |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 687 | #mbox-cells = <1>; |
| 688 | }; |
| 689 | |
| 690 | a53pll: clock@b116000 { |
| 691 | compatible = "qcom,ipq6018-a53pll"; |
| 692 | reg = <0x0 0x0b116000 0x0 0x40>; |
| 693 | #clock-cells = <0>; |
| 694 | clocks = <&xo>; |
| 695 | clock-names = "xo"; |
| 696 | }; |
| 697 | |
| 698 | timer@b120000 { |
| 699 | #address-cells = <1>; |
| 700 | #size-cells = <1>; |
| 701 | ranges = <0 0 0 0x10000000>; |
| 702 | compatible = "arm,armv7-timer-mem"; |
| 703 | reg = <0x0 0x0b120000 0x0 0x1000>; |
| 704 | |
| 705 | frame@b120000 { |
| 706 | frame-number = <0>; |
| 707 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 708 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 709 | reg = <0x0b121000 0x1000>, |
| 710 | <0x0b122000 0x1000>; |
| 711 | }; |
| 712 | |
| 713 | frame@b123000 { |
| 714 | frame-number = <1>; |
| 715 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 716 | reg = <0x0b123000 0x1000>; |
| 717 | status = "disabled"; |
| 718 | }; |
| 719 | |
| 720 | frame@b124000 { |
| 721 | frame-number = <2>; |
| 722 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 723 | reg = <0x0b124000 0x1000>; |
| 724 | status = "disabled"; |
| 725 | }; |
| 726 | |
| 727 | frame@b125000 { |
| 728 | frame-number = <3>; |
| 729 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 730 | reg = <0x0b125000 0x1000>; |
| 731 | status = "disabled"; |
| 732 | }; |
| 733 | |
| 734 | frame@b126000 { |
| 735 | frame-number = <4>; |
| 736 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 737 | reg = <0x0b126000 0x1000>; |
| 738 | status = "disabled"; |
| 739 | }; |
| 740 | |
| 741 | frame@b127000 { |
| 742 | frame-number = <5>; |
| 743 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 744 | reg = <0x0b127000 0x1000>; |
| 745 | status = "disabled"; |
| 746 | }; |
| 747 | |
| 748 | frame@b128000 { |
| 749 | frame-number = <6>; |
| 750 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 751 | reg = <0x0b128000 0x1000>; |
| 752 | status = "disabled"; |
| 753 | }; |
| 754 | }; |
| 755 | |
| 756 | q6v5_wcss: remoteproc@cd00000 { |
| 757 | compatible = "qcom,ipq6018-wcss-pil"; |
| 758 | reg = <0x0 0x0cd00000 0x0 0x4040>, |
| 759 | <0x0 0x004ab000 0x0 0x20>; |
| 760 | reg-names = "qdsp6", |
| 761 | "rmb"; |
| 762 | interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, |
| 763 | <&wcss_smp2p_in 0 0>, |
| 764 | <&wcss_smp2p_in 1 0>, |
| 765 | <&wcss_smp2p_in 2 0>, |
| 766 | <&wcss_smp2p_in 3 0>; |
| 767 | interrupt-names = "wdog", |
| 768 | "fatal", |
| 769 | "ready", |
| 770 | "handover", |
| 771 | "stop-ack"; |
| 772 | |
| 773 | resets = <&gcc GCC_WCSSAON_RESET>, |
| 774 | <&gcc GCC_WCSS_BCR>, |
| 775 | <&gcc GCC_WCSS_Q6_BCR>; |
| 776 | |
| 777 | reset-names = "wcss_aon_reset", |
| 778 | "wcss_reset", |
| 779 | "wcss_q6_reset"; |
| 780 | |
| 781 | clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| 782 | clock-names = "prng"; |
| 783 | |
| 784 | qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; |
| 785 | |
| 786 | qcom,smem-states = <&wcss_smp2p_out 0>, |
| 787 | <&wcss_smp2p_out 1>; |
| 788 | qcom,smem-state-names = "shutdown", |
| 789 | "stop"; |
| 790 | |
| 791 | memory-region = <&q6_region>; |
| 792 | |
| 793 | glink-edge { |
| 794 | interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; |
| 795 | label = "rtr"; |
| 796 | qcom,remote-pid = <1>; |
| 797 | mboxes = <&apcs_glb 8>; |
| 798 | |
| 799 | qrtr_requests { |
| 800 | qcom,glink-channels = "IPCRTR"; |
| 801 | }; |
| 802 | }; |
| 803 | }; |
| 804 | |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 805 | pcie0: pcie@20000000 { |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 806 | compatible = "qcom,pcie-ipq6018"; |
| 807 | reg = <0x0 0x20000000 0x0 0xf1d>, |
| 808 | <0x0 0x20000f20 0x0 0xa8>, |
| 809 | <0x0 0x20001000 0x0 0x1000>, |
| 810 | <0x0 0x80000 0x0 0x4000>, |
| 811 | <0x0 0x20100000 0x0 0x1000>; |
| 812 | reg-names = "dbi", "elbi", "atu", "parf", "config"; |
| 813 | |
| 814 | device_type = "pci"; |
| 815 | linux,pci-domain = <0>; |
| 816 | bus-range = <0x00 0xff>; |
| 817 | num-lanes = <1>; |
| 818 | max-link-speed = <3>; |
| 819 | #address-cells = <3>; |
| 820 | #size-cells = <2>; |
| 821 | |
| 822 | phys = <&pcie_phy>; |
| 823 | phy-names = "pciephy"; |
| 824 | |
| 825 | ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, |
| 826 | <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; |
| 827 | |
| 828 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| 829 | interrupt-names = "msi"; |
| 830 | |
| 831 | #interrupt-cells = <1>; |
| 832 | interrupt-map-mask = <0 0 0 0x7>; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 833 | interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| 834 | <0 0 0 2 &intc 0 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| 835 | <0 0 0 3 &intc 0 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| 836 | <0 0 0 4 &intc 0 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 837 | |
| 838 | clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, |
| 839 | <&gcc GCC_PCIE0_AXI_M_CLK>, |
| 840 | <&gcc GCC_PCIE0_AXI_S_CLK>, |
| 841 | <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, |
| 842 | <&gcc PCIE0_RCHNG_CLK>; |
| 843 | clock-names = "iface", |
| 844 | "axi_m", |
| 845 | "axi_s", |
| 846 | "axi_bridge", |
| 847 | "rchng"; |
| 848 | |
| 849 | resets = <&gcc GCC_PCIE0_PIPE_ARES>, |
| 850 | <&gcc GCC_PCIE0_SLEEP_ARES>, |
| 851 | <&gcc GCC_PCIE0_CORE_STICKY_ARES>, |
| 852 | <&gcc GCC_PCIE0_AXI_MASTER_ARES>, |
| 853 | <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, |
| 854 | <&gcc GCC_PCIE0_AHB_ARES>, |
| 855 | <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, |
| 856 | <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; |
| 857 | reset-names = "pipe", |
| 858 | "sleep", |
| 859 | "sticky", |
| 860 | "axi_m", |
| 861 | "axi_s", |
| 862 | "ahb", |
| 863 | "axi_m_sticky", |
| 864 | "axi_s_sticky"; |
| 865 | |
| 866 | status = "disabled"; |
| 867 | }; |
| 868 | }; |
| 869 | |
| 870 | timer { |
| 871 | compatible = "arm,armv8-timer"; |
| 872 | interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 873 | <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 874 | <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 875 | <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 876 | }; |
| 877 | |
| 878 | wcss: wcss-smp2p { |
| 879 | compatible = "qcom,smp2p"; |
| 880 | qcom,smem = <435>, <428>; |
| 881 | |
| 882 | interrupt-parent = <&intc>; |
| 883 | interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; |
| 884 | |
| 885 | mboxes = <&apcs_glb 9>; |
| 886 | |
| 887 | qcom,local-pid = <0>; |
| 888 | qcom,remote-pid = <1>; |
| 889 | |
| 890 | wcss_smp2p_out: master-kernel { |
| 891 | qcom,entry-name = "master-kernel"; |
| 892 | #qcom,smem-state-cells = <1>; |
| 893 | }; |
| 894 | |
| 895 | wcss_smp2p_in: slave-kernel { |
| 896 | qcom,entry-name = "slave-kernel"; |
| 897 | interrupt-controller; |
| 898 | #interrupt-cells = <2>; |
| 899 | }; |
| 900 | }; |
| 901 | }; |