blob: dbba780c9b0213ee08bb9ed7568431bce200aeef [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence TTC - Triple Timer Counter
8
9maintainers:
10 - Michal Simek <michal.simek@amd.com>
11
12properties:
13 compatible:
14 const: cdns,ttc
15
16 reg:
17 maxItems: 1
18
19 interrupts:
20 maxItems: 3
21 description: |
22 A list of 3 interrupts; one per timer channel.
23
24 clocks:
25 maxItems: 1
26
27 power-domains:
28 maxItems: 1
29
30 timer-width:
31 $ref: /schemas/types.yaml#/definitions/uint32
32 description: |
33 Bit width of the timer, necessary if not 16.
34
35required:
36 - compatible
37 - reg
38 - interrupts
39 - clocks
40
41additionalProperties: false
42
43examples:
44 - |
45 ttc0: ttc0@f8001000 {
46 interrupt-parent = <&intc>;
47 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
48 compatible = "cdns,ttc";
49 reg = <0xF8001000 0x1000>;
50 clocks = <&cpu_clk 3>;
51 timer-width = <32>;
52 };