blob: c0398b91166a32260233e5aa4803008fd598cddd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek72536fd2015-11-20 13:17:22 +01002/*
3 * Copyright 2015 - 2016 Xilinx, Inc.
4 *
5 * Michal Simek <michal.simek@xilinx.com>
Michal Simek72536fd2015-11-20 13:17:22 +01006 */
7
8#include <common.h>
9#include <debug_uart.h>
Simon Glassa7b51302019-11-14 12:57:46 -070010#include <init.h>
Michal Simek72536fd2015-11-20 13:17:22 +010011#include <spl.h>
12
13#include <asm/io.h>
14#include <asm/spl.h>
15#include <asm/arch/hardware.h>
Michal Simekef955012019-12-03 15:02:50 +010016#include <asm/arch/psu_init_gpl.h>
Michal Simek72536fd2015-11-20 13:17:22 +010017#include <asm/arch/sys_proto.h>
18
19void board_init_f(ulong dummy)
20{
Michal Simeke0f36102017-07-12 13:08:41 +020021 board_early_init_f();
Michal Simek72536fd2015-11-20 13:17:22 +010022 board_early_init_r();
23
24#ifdef CONFIG_DEBUG_UART
25 /* Uart debug for sure */
26 debug_uart_init();
27 puts("Debug uart enabled\n"); /* or printch() */
28#endif
29 /* Delay is required for clocks to be propagated */
30 udelay(1000000);
Michal Simek72536fd2015-11-20 13:17:22 +010031}
32
Michal Simek3eb32de2016-08-15 09:41:36 +020033static void ps_mode_reset(ulong mode)
34{
Michal Simek3eb32de2016-08-15 09:41:36 +020035 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
36 &crlapb_base->boot_pin_ctrl);
37 udelay(5);
38 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
39 mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
40 &crlapb_base->boot_pin_ctrl);
41}
42
43/*
44 * Set default PS_MODE1 which is used for USB ULPI phy reset
45 * Also other resets can be connected to this certain pin
46 */
47#ifndef MODE_RESET
48# define MODE_RESET PS_MODE1
49#endif
50
Michal Simek72536fd2015-11-20 13:17:22 +010051#ifdef CONFIG_SPL_BOARD_INIT
52void spl_board_init(void)
53{
54 preloader_console_init();
Michal Simek3eb32de2016-08-15 09:41:36 +020055 ps_mode_reset(MODE_RESET);
Michal Simek72536fd2015-11-20 13:17:22 +010056 board_init();
Michal Simekef955012019-12-03 15:02:50 +010057 psu_post_config_data();
Michal Simek72536fd2015-11-20 13:17:22 +010058}
59#endif
60
Michal Simek6d651d92019-12-09 13:00:57 +010061void board_boot_order(u32 *spl_boot_list)
62{
63 spl_boot_list[0] = spl_boot_device();
64
65 if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
66 spl_boot_list[1] = BOOT_DEVICE_MMC2;
67 if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
68 spl_boot_list[1] = BOOT_DEVICE_MMC1;
69}
70
Michal Simek72536fd2015-11-20 13:17:22 +010071u32 spl_boot_device(void)
72{
73 u32 reg = 0;
74 u8 bootmode;
75
Michal Simek94ddcaa2016-08-30 16:17:27 +020076#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
77 /* Change default boot mode at run-time */
Michal Simek833e0c42016-10-25 11:43:02 +020078 writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
Michal Simek94ddcaa2016-08-30 16:17:27 +020079 &crlapb_base->boot_mode);
80#endif
81
Michal Simek72536fd2015-11-20 13:17:22 +010082 reg = readl(&crlapb_base->boot_mode);
Michal Simek833e0c42016-10-25 11:43:02 +020083 if (reg >> BOOT_MODE_ALT_SHIFT)
84 reg >>= BOOT_MODE_ALT_SHIFT;
85
Michal Simek72536fd2015-11-20 13:17:22 +010086 bootmode = reg & BOOT_MODES_MASK;
87
88 switch (bootmode) {
89 case JTAG_MODE:
90 return BOOT_DEVICE_RAM;
91#ifdef CONFIG_SPL_MMC_SUPPORT
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -040092 case SD_MODE1:
Michal Simeka8896202017-03-02 11:02:55 +010093 case SD1_LSHFT_MODE: /* not working on silicon v1 */
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -040094 return BOOT_DEVICE_MMC2;
Michal Simek72536fd2015-11-20 13:17:22 +010095 case SD_MODE:
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -040096 case EMMC_MODE:
Michal Simek72536fd2015-11-20 13:17:22 +010097 return BOOT_DEVICE_MMC1;
98#endif
Andrew F. Davis6d932e62019-01-17 13:43:02 -060099#ifdef CONFIG_SPL_DFU
Michal Simek12398ea2016-08-19 14:14:52 +0200100 case USB_MODE:
101 return BOOT_DEVICE_DFU;
102#endif
Michal Simek2740d372016-10-26 09:24:32 +0200103#ifdef CONFIG_SPL_SATA_SUPPORT
104 case SW_SATA_MODE:
105 return BOOT_DEVICE_SATA;
106#endif
Michal Simek1b19a6f2017-11-02 09:15:05 +0100107#ifdef CONFIG_SPL_SPI_SUPPORT
108 case QSPI_MODE_24BIT:
109 case QSPI_MODE_32BIT:
110 return BOOT_DEVICE_SPI;
111#endif
Michal Simek72536fd2015-11-20 13:17:22 +0100112 default:
113 printf("Invalid Boot Mode:0x%x\n", bootmode);
114 break;
115 }
116
117 return 0;
118}
119
Michal Simek72536fd2015-11-20 13:17:22 +0100120#ifdef CONFIG_SPL_OS_BOOT
121int spl_start_uboot(void)
122{
Michal Simek456e4542017-01-09 10:05:16 +0100123 handoff_setup();
124
Michal Simek72536fd2015-11-20 13:17:22 +0100125 return 0;
126}
127#endif
128
129#ifdef CONFIG_SPL_LOAD_FIT
130int board_fit_config_name_match(const char *name)
131{
132 /* Just empty function now - can't decide what to choose */
133 debug("%s: %s\n", __func__, name);
134
135 return 0;
136}
137#endif