| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC |
| 4 | * |
| 5 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> |
| 6 | */ |
| 7 | |
| 8 | / { |
| 9 | #address-cells = <1>; |
| 10 | #size-cells = <1>; |
| 11 | compatible = "wm,wm8505"; |
| 12 | |
| 13 | cpus { |
| 14 | #address-cells = <0>; |
| 15 | #size-cells = <0>; |
| 16 | |
| 17 | cpu { |
| 18 | device_type = "cpu"; |
| 19 | compatible = "arm,arm926ej-s"; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | memory { |
| 24 | device_type = "memory"; |
| 25 | reg = <0x0 0x0>; |
| 26 | }; |
| 27 | |
| 28 | aliases { |
| 29 | serial0 = &uart0; |
| 30 | serial1 = &uart1; |
| 31 | serial2 = &uart2; |
| 32 | serial3 = &uart3; |
| 33 | serial4 = &uart4; |
| 34 | serial5 = &uart5; |
| 35 | }; |
| 36 | |
| 37 | soc { |
| 38 | #address-cells = <1>; |
| 39 | #size-cells = <1>; |
| 40 | compatible = "simple-bus"; |
| 41 | ranges; |
| 42 | interrupt-parent = <&intc0>; |
| 43 | |
| 44 | intc0: interrupt-controller@d8140000 { |
| 45 | compatible = "via,vt8500-intc"; |
| 46 | interrupt-controller; |
| 47 | reg = <0xd8140000 0x10000>; |
| 48 | #interrupt-cells = <1>; |
| 49 | }; |
| 50 | |
| 51 | /* Secondary IC cascaded to intc0 */ |
| 52 | intc1: interrupt-controller@d8150000 { |
| 53 | compatible = "via,vt8500-intc"; |
| 54 | interrupt-controller; |
| 55 | #interrupt-cells = <1>; |
| 56 | reg = <0xD8150000 0x10000>; |
| 57 | interrupts = <56 57 58 59 60 61 62 63>; |
| 58 | }; |
| 59 | |
| 60 | pinctrl: pinctrl@d8110000 { |
| 61 | compatible = "wm,wm8505-pinctrl"; |
| 62 | reg = <0xd8110000 0x10000>; |
| 63 | interrupt-controller; |
| 64 | #interrupt-cells = <2>; |
| 65 | gpio-controller; |
| 66 | #gpio-cells = <2>; |
| 67 | }; |
| 68 | |
| 69 | pmc@d8130000 { |
| 70 | compatible = "via,vt8500-pmc"; |
| 71 | reg = <0xd8130000 0x1000>; |
| 72 | clocks { |
| 73 | #address-cells = <1>; |
| 74 | #size-cells = <0>; |
| 75 | |
| 76 | ref24: ref24M { |
| 77 | #clock-cells = <0>; |
| 78 | compatible = "fixed-clock"; |
| 79 | clock-frequency = <24000000>; |
| 80 | }; |
| 81 | |
| 82 | ref25: ref25M { |
| 83 | #clock-cells = <0>; |
| 84 | compatible = "fixed-clock"; |
| 85 | clock-frequency = <25000000>; |
| 86 | }; |
| 87 | |
| 88 | plla: plla { |
| 89 | #clock-cells = <0>; |
| 90 | compatible = "via,vt8500-pll-clock"; |
| 91 | clocks = <&ref25>; |
| 92 | reg = <0x200>; |
| 93 | }; |
| 94 | |
| 95 | pllb: pllb { |
| 96 | #clock-cells = <0>; |
| 97 | compatible = "via,vt8500-pll-clock"; |
| 98 | clocks = <&ref25>; |
| 99 | reg = <0x204>; |
| 100 | }; |
| 101 | |
| 102 | pllc: pllc { |
| 103 | #clock-cells = <0>; |
| 104 | compatible = "via,vt8500-pll-clock"; |
| 105 | clocks = <&ref25>; |
| 106 | reg = <0x208>; |
| 107 | }; |
| 108 | |
| 109 | plld: plld { |
| 110 | #clock-cells = <0>; |
| 111 | compatible = "via,vt8500-pll-clock"; |
| 112 | clocks = <&ref25>; |
| 113 | reg = <0x20c>; |
| 114 | }; |
| 115 | |
| 116 | clkarm: arm { |
| 117 | #clock-cells = <0>; |
| 118 | compatible = "via,vt8500-device-clock"; |
| 119 | clocks = <&plla>; |
| 120 | divisor-reg = <0x300>; |
| 121 | }; |
| 122 | |
| 123 | clkahb: ahb { |
| 124 | #clock-cells = <0>; |
| 125 | compatible = "via,vt8500-device-clock"; |
| 126 | clocks = <&pllb>; |
| 127 | divisor-reg = <0x304>; |
| 128 | }; |
| 129 | |
| 130 | clkapb: apb { |
| 131 | #clock-cells = <0>; |
| 132 | compatible = "via,vt8500-device-clock"; |
| 133 | clocks = <&pllb>; |
| 134 | divisor-reg = <0x350>; |
| 135 | }; |
| 136 | |
| 137 | clkddr: ddr { |
| 138 | #clock-cells = <0>; |
| 139 | compatible = "via,vt8500-device-clock"; |
| 140 | clocks = <&plld>; |
| 141 | divisor-reg = <0x310>; |
| 142 | }; |
| 143 | |
| 144 | clkuart0: uart0 { |
| 145 | #clock-cells = <0>; |
| 146 | compatible = "via,vt8500-device-clock"; |
| 147 | clocks = <&ref24>; |
| 148 | enable-reg = <0x250>; |
| 149 | enable-bit = <1>; |
| 150 | }; |
| 151 | |
| 152 | clkuart1: uart1 { |
| 153 | #clock-cells = <0>; |
| 154 | compatible = "via,vt8500-device-clock"; |
| 155 | clocks = <&ref24>; |
| 156 | enable-reg = <0x250>; |
| 157 | enable-bit = <2>; |
| 158 | }; |
| 159 | |
| 160 | clkuart2: uart2 { |
| 161 | #clock-cells = <0>; |
| 162 | compatible = "via,vt8500-device-clock"; |
| 163 | clocks = <&ref24>; |
| 164 | enable-reg = <0x250>; |
| 165 | enable-bit = <3>; |
| 166 | }; |
| 167 | |
| 168 | clkuart3: uart3 { |
| 169 | #clock-cells = <0>; |
| 170 | compatible = "via,vt8500-device-clock"; |
| 171 | clocks = <&ref24>; |
| 172 | enable-reg = <0x250>; |
| 173 | enable-bit = <4>; |
| 174 | }; |
| 175 | |
| 176 | clkuart4: uart4 { |
| 177 | #clock-cells = <0>; |
| 178 | compatible = "via,vt8500-device-clock"; |
| 179 | clocks = <&ref24>; |
| 180 | enable-reg = <0x250>; |
| 181 | enable-bit = <22>; |
| 182 | }; |
| 183 | |
| 184 | clkuart5: uart5 { |
| 185 | #clock-cells = <0>; |
| 186 | compatible = "via,vt8500-device-clock"; |
| 187 | clocks = <&ref24>; |
| 188 | enable-reg = <0x250>; |
| 189 | enable-bit = <23>; |
| 190 | }; |
| 191 | |
| 192 | clksdhc: sdhc { |
| 193 | #clock-cells = <0>; |
| 194 | compatible = "via,vt8500-device-clock"; |
| 195 | clocks = <&pllb>; |
| 196 | divisor-reg = <0x328>; |
| 197 | divisor-mask = <0x3f>; |
| 198 | enable-reg = <0x254>; |
| 199 | enable-bit = <18>; |
| 200 | }; |
| 201 | }; |
| 202 | }; |
| 203 | |
| 204 | timer@d8130100 { |
| 205 | compatible = "via,vt8500-timer"; |
| 206 | reg = <0xd8130100 0x28>; |
| 207 | interrupts = <36>; |
| 208 | }; |
| 209 | |
| 210 | ehci@d8007100 { |
| 211 | compatible = "via,vt8500-ehci"; |
| 212 | reg = <0xd8007100 0x200>; |
| 213 | interrupts = <1>; |
| 214 | }; |
| 215 | |
| 216 | uhci@d8007300 { |
| 217 | compatible = "platform-uhci"; |
| 218 | reg = <0xd8007300 0x200>; |
| 219 | interrupts = <0>; |
| 220 | }; |
| 221 | |
| 222 | fb: fb@d8050800 { |
| 223 | compatible = "wm,wm8505-fb"; |
| 224 | reg = <0xd8050800 0x200>; |
| 225 | }; |
| 226 | |
| 227 | ge_rops@d8050400 { |
| 228 | compatible = "wm,prizm-ge-rops"; |
| 229 | reg = <0xd8050400 0x100>; |
| 230 | }; |
| 231 | |
| 232 | uart0: serial@d8200000 { |
| 233 | compatible = "via,vt8500-uart"; |
| 234 | reg = <0xd8200000 0x1040>; |
| 235 | interrupts = <32>; |
| 236 | clocks = <&clkuart0>; |
| 237 | status = "disabled"; |
| 238 | }; |
| 239 | |
| 240 | uart1: serial@d82b0000 { |
| 241 | compatible = "via,vt8500-uart"; |
| 242 | reg = <0xd82b0000 0x1040>; |
| 243 | interrupts = <33>; |
| 244 | clocks = <&clkuart1>; |
| 245 | status = "disabled"; |
| 246 | }; |
| 247 | |
| 248 | uart2: serial@d8210000 { |
| 249 | compatible = "via,vt8500-uart"; |
| 250 | reg = <0xd8210000 0x1040>; |
| 251 | interrupts = <47>; |
| 252 | clocks = <&clkuart2>; |
| 253 | status = "disabled"; |
| 254 | }; |
| 255 | |
| 256 | uart3: serial@d82c0000 { |
| 257 | compatible = "via,vt8500-uart"; |
| 258 | reg = <0xd82c0000 0x1040>; |
| 259 | interrupts = <50>; |
| 260 | clocks = <&clkuart3>; |
| 261 | status = "disabled"; |
| 262 | }; |
| 263 | |
| 264 | uart4: serial@d8370000 { |
| 265 | compatible = "via,vt8500-uart"; |
| 266 | reg = <0xd8370000 0x1040>; |
| 267 | interrupts = <31>; |
| 268 | clocks = <&clkuart4>; |
| 269 | status = "disabled"; |
| 270 | }; |
| 271 | |
| 272 | uart5: serial@d8380000 { |
| 273 | compatible = "via,vt8500-uart"; |
| 274 | reg = <0xd8380000 0x1040>; |
| 275 | interrupts = <30>; |
| 276 | clocks = <&clkuart5>; |
| 277 | status = "disabled"; |
| 278 | }; |
| 279 | |
| 280 | rtc@d8100000 { |
| 281 | compatible = "via,vt8500-rtc"; |
| 282 | reg = <0xd8100000 0x10000>; |
| 283 | interrupts = <48>; |
| 284 | }; |
| 285 | |
| 286 | sdhc@d800a000 { |
| 287 | compatible = "wm,wm8505-sdhc"; |
| 288 | reg = <0xd800a000 0x400>; |
| 289 | interrupts = <20>, <21>; |
| 290 | clocks = <&clksdhc>; |
| 291 | bus-width = <4>; |
| 292 | }; |
| 293 | }; |
| 294 | }; |