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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala38449a42009-09-10 03:02:13 -05002/*
Haiying Wang325a12f2011-01-20 22:26:31 +00003 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala38449a42009-09-10 03:02:13 -05004 */
5
6#ifndef _FSL_LIODN_H_
7#define _FSL_LIODN_H_
8
9#include <asm/types.h>
Ahmed Mansouraa270b42017-12-15 16:01:00 -050010#include <fsl_qbman.h>
Kumar Gala38449a42009-09-10 03:02:13 -050011
Kumar Gala2b2b6962011-10-14 00:01:23 -050012struct srio_liodn_id_table {
13 u32 id[2];
14 unsigned long reg_offset[2];
15 u8 num_ids;
16 u8 portid;
17};
18#define SET_SRIO_LIODN_1(port, idA) \
19 { .id = { idA }, .num_ids = 1, .portid = port, \
20 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
Tom Rinid5c3bf22022-10-28 20:27:12 -040021 + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
Kumar Gala2b2b6962011-10-14 00:01:23 -050022 }
23
24#define SET_SRIO_LIODN_2(port, idA, idB) \
25 { .id = { idA, idB }, .num_ids = 2, .portid = port, \
26 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
Tom Rinid5c3bf22022-10-28 20:27:12 -040027 + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
Kumar Gala2b2b6962011-10-14 00:01:23 -050028 .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
Tom Rinid5c3bf22022-10-28 20:27:12 -040029 + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
Kumar Gala2b2b6962011-10-14 00:01:23 -050030 }
31
Liu Gang1d5284b2013-06-25 18:12:12 +080032#define SET_SRIO_LIODN_BASE(port, id_a) \
33 { .id = { id_a }, .num_ids = 1, .portid = port, \
34 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
35 + (port - 1) * 0x200 \
Tom Rini376b88a2022-10-28 20:27:13 -040036 + CFG_SYS_FSL_SRIO_ADDR, \
Liu Gang1d5284b2013-06-25 18:12:12 +080037 }
38
Kumar Gala38449a42009-09-10 03:02:13 -050039struct liodn_id_table {
40 const char * compat;
41 u32 id[2];
42 u8 num_ids;
43 phys_addr_t compat_offset;
44 unsigned long reg_offset;
45};
46
Igal Libermane14ec992015-08-18 14:47:05 +030047struct fman_liodn_id_table {
48 /* Freescale FMan Device Tree binding was updated for FMan.
49 * We need to support both new and old compatibles in order not to
50 * break backward compatibility.
51 */
52 const char *compat[2];
53 u32 id[2];
54 u8 num_ids;
55 phys_addr_t compat_offset;
56 unsigned long reg_offset;
57};
58
Kumar Gala38449a42009-09-10 03:02:13 -050059extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid);
60extern void set_liodns(void);
61extern void fdt_fixup_liodn(void *blob);
62
63#define SET_LIODN_BASE_1(idA) \
64 { .id = { idA }, .num_ids = 1, }
65
66#define SET_LIODN_BASE_2(idA, idB) \
67 { .id = { idA, idB }, .num_ids = 2 }
68
Igal Libermane14ec992015-08-18 14:47:05 +030069#define SET_FMAN_LIODN_ENTRY(name1, name2, idA, off, compatoff)\
70 { .compat[0] = name1, \
71 .compat[1] = name2, \
72 .id = { idA }, .num_ids = 1, \
73 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
74 .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
75 }
76
Kumar Gala38449a42009-09-10 03:02:13 -050077#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
78 { .compat = name, \
79 .id = { idA }, .num_ids = 1, \
80 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
81 .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
82 }
83
84#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
85 { .compat = name, \
86 .id = { idA, idB }, .num_ids = 2, \
87 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
88 .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
89 }
90
91#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
92 SET_LIODN_ENTRY_1(compat, liodn, \
Tom Rinid5c3bf22022-10-28 20:27:12 -040093 offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
Kumar Gala38449a42009-09-10 03:02:13 -050094 compatoff)
95
96#define SET_USB_LIODN(usbNum, compat, liodn) \
97 SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -040098 CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -050099
100#define SET_SATA_LIODN(sataNum, liodn) \
101 SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400102 CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500103
Laurentiu TUDOR960f87f2011-03-15 16:37:36 +0200104#define SET_PCI_LIODN(compat, pciNum, liodn) \
105 SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400106 CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500107
Laurentiu Tudorb173eaf2012-10-05 09:48:51 +0000108#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
109 SET_LIODN_ENTRY_1(compat, liodn,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400110 offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
111 CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
Laurentiu Tudorb173eaf2012-10-05 09:48:51 +0000112
Kumar Gala38449a42009-09-10 03:02:13 -0500113/* reg nodes for DMA start @ 0x300 */
Tudor Laurentiu7210d9a2014-11-20 12:09:31 +0200114#define SET_DMA_LIODN(dmaNum, compat, liodn) \
115 SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400116 CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
Kumar Gala38449a42009-09-10 03:02:13 -0500117
118#define SET_SDHC_LIODN(sdhcNum, liodn) \
119 SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400120 CFG_SYS_MPC85xx_ESDHC_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500121
Zhao Qiangb818ba22014-03-21 16:21:45 +0800122#define SET_QE_LIODN(liodn) \
123 SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400124 CFG_SYS_MPC85xx_QE_OFFSET)
Zhao Qiangb818ba22014-03-21 16:21:45 +0800125
Sandeep Singh4fb16a12014-06-05 18:49:57 +0530126#define SET_TDM_LIODN(liodn) \
127 SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400128 CFG_SYS_MPC85xx_TDM_OFFSET)
Sandeep Singh4fb16a12014-06-05 18:49:57 +0530129
Kumar Gala38449a42009-09-10 03:02:13 -0500130#define SET_QMAN_LIODN(liodn) \
Ahmed Mansouraa270b42017-12-15 16:01:00 -0500131 SET_LIODN_ENTRY_1("fsl,qman", liodn, \
132 offsetof(struct ccsr_qman, liodnr) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400133 CFG_SYS_FSL_QMAN_OFFSET, \
134 CFG_SYS_FSL_QMAN_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500135
136#define SET_BMAN_LIODN(liodn) \
Ahmed Mansouraa270b42017-12-15 16:01:00 -0500137 SET_LIODN_ENTRY_1("fsl,bman", liodn, \
138 offsetof(struct ccsr_bman, liodnr) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400139 CFG_SYS_FSL_BMAN_OFFSET, \
140 CFG_SYS_FSL_BMAN_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500141
142#define SET_PME_LIODN(liodn) \
143 SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400144 CFG_SYS_FSL_CORENET_PME_OFFSET, \
145 CFG_SYS_FSL_CORENET_PME_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500146
Andy Fleming81177ad2012-10-08 07:44:18 +0000147#define SET_PMAN_LIODN(num, liodn) \
148 SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
149 offsetof(struct ccsr_pman, ppa1) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400150 CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
151 CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
Andy Fleming81177ad2012-10-08 07:44:18 +0000152
Kumar Gala38449a42009-09-10 03:02:13 -0500153/* -1 from portID due to how immap has the registers */
154#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
Tom Rini376b88a2022-10-28 20:27:13 -0400155 CFG_SYS_FSL_FM##fmNum##_OFFSET + \
Kumar Gala38449a42009-09-10 03:02:13 -0500156 offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
157
Igal Libermane14ec992015-08-18 14:47:05 +0300158#ifdef CONFIG_SYS_FMAN_V3
Kumar Gala38449a42009-09-10 03:02:13 -0500159/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
160#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
Igal Libermane14ec992015-08-18 14:47:05 +0300161 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
162 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
Tom Rini376b88a2022-10-28 20:27:13 -0400163 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500164
165/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
166#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
Igal Libermane14ec992015-08-18 14:47:05 +0300167 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
168 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
Tom Rini376b88a2022-10-28 20:27:13 -0400169 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500170
Shengzhou Liu0e24d3a2015-05-14 16:51:39 +0800171/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
172#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
Igal Libermane14ec992015-08-18 14:47:05 +0300173 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
174 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
Tom Rini376b88a2022-10-28 20:27:13 -0400175 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
Igal Libermane14ec992015-08-18 14:47:05 +0300176#else
177/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
178#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
179 SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
180 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
Tom Rini376b88a2022-10-28 20:27:13 -0400181 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
Shengzhou Liu0e24d3a2015-05-14 16:51:39 +0800182
Igal Libermane14ec992015-08-18 14:47:05 +0300183/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
184#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
185 SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
186 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
Tom Rini376b88a2022-10-28 20:27:13 -0400187 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
Igal Libermane14ec992015-08-18 14:47:05 +0300188#endif
Kim Phillipse49f1c32011-04-12 14:12:47 -0500189/*
190 * handle both old and new versioned SEC properties:
191 * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
192 */
Kumar Gala1c9cee92010-08-17 23:12:37 -0500193#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
194 SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
195 offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400196 CFG_SYS_FSL_SEC_OFFSET, \
197 CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
Kim Phillipse49f1c32011-04-12 14:12:47 -0500198 SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
199 offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400200 CFG_SYS_FSL_SEC_OFFSET, \
201 CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
Kumar Gala38449a42009-09-10 03:02:13 -0500202
203/* This is a bit evil since we treat rtic param as both a string & hex value */
204#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
205 SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
206 liodnA, \
207 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400208 CFG_SYS_FSL_SEC_OFFSET, \
209 CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
Kim Phillipse49f1c32011-04-12 14:12:47 -0500210 SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
211 liodnA, \
212 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400213 CFG_SYS_FSL_SEC_OFFSET, \
214 CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
Kumar Gala38449a42009-09-10 03:02:13 -0500215
216#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
217 SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
218 offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400219 CFG_SYS_FSL_SEC_OFFSET, 0)
Kumar Gala38449a42009-09-10 03:02:13 -0500220
Kumar Gala9d8e8132011-09-10 10:44:13 -0500221#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
222 SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
223 liodnA, \
224 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400225 CFG_SYS_FSL_RAID_ENGINE_OFFSET, \
Kumar Gala9d8e8132011-09-10 10:44:13 -0500226 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400227 CFG_SYS_FSL_RAID_ENGINE_OFFSET)
Kumar Gala9d8e8132011-09-10 10:44:13 -0500228
Kumar Gala4eb3c372011-10-14 13:28:52 -0500229#define SET_RMAN_LIODN(ibNum, liodn) \
230 SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
231 offsetof(struct ccsr_rman, mmitdr) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400232 CFG_SYS_FSL_CORENET_RMAN_OFFSET, \
233 CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
Kumar Gala4eb3c372011-10-14 13:28:52 -0500234
Kumar Gala38449a42009-09-10 03:02:13 -0500235extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
Kumar Gala9d8e8132011-09-10 10:44:13 -0500236extern struct liodn_id_table raide_liodn_tbl[];
Igal Libermane14ec992015-08-18 14:47:05 +0300237extern struct fman_liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
Timur Tabiebede502012-10-05 09:48:52 +0000238#ifdef CONFIG_SYS_SRIO
Kumar Gala2b2b6962011-10-14 00:01:23 -0500239extern struct srio_liodn_id_table srio_liodn_tbl[];
Timur Tabiebede502012-10-05 09:48:52 +0000240extern int srio_liodn_tbl_sz;
241#endif
Kumar Gala4eb3c372011-10-14 13:28:52 -0500242extern struct liodn_id_table rman_liodn_tbl[];
Kumar Gala9d8e8132011-09-10 10:44:13 -0500243extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
Kumar Gala38449a42009-09-10 03:02:13 -0500244extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
Kumar Gala4eb3c372011-10-14 13:28:52 -0500245extern int rman_liodn_tbl_sz;
Kumar Gala38449a42009-09-10 03:02:13 -0500246
247#endif